Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs
01 Nov 2014-pp 32-33
TL;DR: This work demonstrates how TFET's device level chracteristics translate into favourable circuit performance metrics, which are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications.
Abstract: This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large I on /I off etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, g m /I ds , BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.
Citations
More filters
TL;DR: The proposedTFET circuit co-design approach enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.
Abstract: Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.
15 citations
TL;DR: In this paper , a detailed Sentaurus TCAD simulation based study for Si-DG TFET based Ring Oscillator (RO) is presented, where two different ring oscillator topologies (simple RO and negative skewed delay RO ) are presented with two different structures for TFET device.
Abstract: A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO )are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).
1 citations
29 Jun 2017
TL;DR: It is clearly evident that TFET buffers exhibit improved speed of operation and high energy efficiency over FinFET buffers for scaled supply voltages, demonstrating suitability for applications such as Internet of things (IoT) SoCs.
Abstract: Energy efficient buffer circuits enable high speed and reliable information transfer among sub-systems of System on Chip (SoC). A novel buffer circuit design exploiting the steep slope characteristics of tunnel FETs (TFET) has been proposed and benchmarked with 20 nm Si FinFET technology. The analysis is performed considering the parameters such as iso-area, iso-energy, iso-speed and noise margins for energy efficiency and reliability. It is clearly evident that TFET buffers exhibit improved speed of operation and high energy efficiency over FinFET buffers for scaled supply voltages, demonstrating suitability for applications such as Internet of things (IoT) SoCs. To further exemplify the buffer circuit performance, TFET/FinFET pass transistor based full adder carry circuit is implemented whose output load is driven by TFET/FinFET buffer. Unlike FinFET buffer circuits, TFET buffers prove to be reliable and energy efficient in driving larger loads despite the area overhead caused due to the unidirectional current conduction of TFETs.
References
More filters
TL;DR: This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting source and proposes architecture for achieving the required ultra-low energy operation.
Abstract: This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting source. These requirements place demands on all levels of the design. We propose architecture for achieving the required ultra-low energy operation and discuss the circuit techniques necessary to implement the system. Dedicated hardware implementations improve the efficiency for specific functionality, and modular partitioning permits fine-grained optimization and power-gating. We describe modeling and operating at the minimum energy point in the subthreshold region for digital circuits. We also examine approaches for improving the energy efficiency of analog components like the transmitter and the ADC. A microsensor node using the techniques we describe can function in an energy-harvesting scenario.
293 citations
TL;DR: In this paper, various configurations of double-gate MOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design.
Abstract: Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.
26 citations