Design and Simulation of Multi Channel UART for Serial Communication
30 Aug 2012-International Journal of Computer Applications (Foundation of Computer Science (FCS))-Vol. 52, Iss: 20, pp 7-10
TL;DR: A multi channel UART is proposed in this paper for serial communication and the whole design is simulated with modelsim and synthesized with Xilinx software.
Abstract: Universal Asynchronous Receiver Transmitter) is used for serial communication. It is used for long distance and low cost process for transfer of data between pc and its devices. In general a UART operated with specific baud rate. To meet the complex communication demands it is not sufficient. To overcome this difficulty a multi channel UART is proposed in this paper. And the whole design is simulated with modelsim and synthesized with Xilinx software KeywordsBaud rate generator, First in First Out, Simulation.
Citations
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TL;DR: In this paper , a multi-channel UART controller is designed with asynchronous FIFO and Baud rate generator and parity generator and verified using simulation waveform of the UART transmitter and receiver and synthesis result is verified in the 14.7 version of Xilinx Software.
Abstract: - A single UART is not sufficient to encounter communication between the modern multipart control systems with dissimilar Baud rates. so, we projected a multi-channel UART controller design method, and BIST technology is included in this paper to overcome the errors. This multi-channel UART controller is designed with Asynchronous FIFO and Baud rate generator and parity generator [1]. This Multi-Channel UART provides communication in complex control systems effectively. The verification of multi-channel UART is verified using the simulation waveform of the UART transmitter and receiver and the synthesis result is verified in the 14.7 version of Xilinx Software [7]
References
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28 May 2011TL;DR: The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission.
Abstract: UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission. It's significant for the design of SOC. The simulation results with Quartus II are completely consistent with the UART protocol.
90 citations
"Design and Simulation of Multi Chan..." refers background in this paper
...This serial communication process is much suited for long distance data transmission because of less transmission lines [2]....
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TL;DR: In this paper, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit.
Abstract: The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have no choice but to accept new responsibilities that had been performed by groups of technicians in the previous years. Design engineers who do not design systems with full testability in mind open themselves to the increased possibility of product failures and missed market opportunities. BIST is a design technique that allows a circuit to test itself. In this paper, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.
30 citations
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TL;DR: By using the Verilog-HDL to describe the three kernel functional modules of the Uart, making them as a whole and simulating them with the Modelsim, the results of the simulation are completely consistent with the UART protocol.
Abstract: The protocol of the UART,a full-duplex data transmission protocol,is widely used in data communication and control systemsIn the industry,it dose not use all the functions of the UART but the coreThere are three kernel functional modules in UART which consists of baud rate generator,receiver and transmitterBy using the Verilog-HDL to describe the three kernel functional modules of the UART,making them as a whole and simulating them with the Modelsim,the results of the simulation are completely consistent with the UART protocol
11 citations
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TL;DR: An improved asynchronous FIFO is proposed, which can generate empty and full flags more correctly while improving the transmission speed and a new approach with easy operation and convenient realization is presented to deal with the fractional frequency division.
Abstract: Based on the FSM theory,the design of an embedded UART is performed in this paper,which supports the interface of an AMBA(Advanced Microcontroller Bus Architecture) 2.0 APB(Advanced Peripheral Bus).An improved asynchronous FIFO is proposed,which can generate empty and full flags more correctly while improving the transmission speed.Also,a new approach with easy operation and convenient realization is presented to deal with the fractional frequency division.It had been tested on FPGA.Embedded in the system,it had realized the transmission of data with that of ARM PSK system at any bit rate within 230 K in the condition of UART clock 12.5 M.Results of the test prove the feasibility of the design.
3 citations