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Proceedings ArticleDOI

Design and use of a system-level specification and verification methodology

01 Dec 1995-pp 490-495

TL;DR: The steps on the way to designing a methodology which captures system level interface and functional specifications, and enables the designers to decompose and refine specifications down to RTL VHDL in a hierarchic and piece-wise manner are described.

AbstractThis paper describes the problem of Design Capture at System level and of moving a design verifiably down levels of abstraction. We describe our steps on the way to designing a methodology which captures system level interface and functional specifications, and enables the designers to decompose and refine specifications down to RTL VHDL in a hierarchic and piece-wise manner.

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Citations
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Book
23 Feb 2007
TL;DR: ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today.
Abstract: Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors! Electronic System Level (ESL) design has mainstreamed --- it is now an established approach at most of the world's leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with `no links to implementation', ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today. Table of Contents CHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS * Provides broad, comprehensive coverage not available in any other such book * Massive global appeal with an internationally recognised author team * Crammed full of state of the art content from notable industry experts

199 citations


Journal ArticleDOI
TL;DR: This paper describes how a model of a system to be implemented using COM might be constructed using a particular modelling tool, RolEnact, and discusses the extent to which validation of the model contributes to the validity of the eventual solution.
Abstract: Software Engineers continue to search for efficient ways to build high quality systems. Two contrasting techniques that promise to help with the effective construction of high quality systems are the use of formal models during design and the use of components during development. In this paper, we take the position that these techniques work well together. Hardware Engineers have shown that building systems from components has brought enormous benefits. Using components permits hardware engineers to consider systems at an abstract level, making it possible for them to build and reason about systems that would otherwise be too large and complex to understand. It also enables them to make effective reuse of existing designs. It seems reasonable to expect that using components in software development will also bring advantages. Formal methods provide a means to reason about a program (or system) enabling the creation of programs which can be proved to meet their specifications. However, the size of real systems makes these methods impractical for any but the simplest of structures — constructing a complete formal specification for a commercial system is a daunting task. Using formal methods for the whole of a large commercial system is not practical, but some of the advantages of using them can be obtained where a system is to be built from communicating components, by building and evaluating a formal model of the system. We describe how a model of a system to be implemented using COM might be constructed using a particular modelling tool, RolEnact. We discuss the extent to which validation of the model contributes to the validity of the eventual solution.

27 citations


Cites background from "Design and use of a system-level sp..."

  • ...We observe that in hardware development, where the use of component technologies is much more widespread than software, extensive use is made of models and simulation of proposed systems [6, 16, 23]....

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Proceedings ArticleDOI
01 Jun 1999
TL;DR: A new design flow that significantly reduces time-to-market for highly complex multiprocessor-based System-On-Chip designs, called Fast Prototyping, that enables concurrent hardware and software development, early verification and productive re-use of intellectual property is described.
Abstract: This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based System-On-Chip designs. This flow, called Fast Prototyping, enables concurrent hardware and software development, early verification and productive re-use of intellectual property. We describe how using this innovative system design flow, that combines different technologies, such as C modeling, emulation, hard virtual component re-use and CoWare N2C/sup TM/. We achieve better productivity on a multi-processor SOC design.

23 citations


Proceedings ArticleDOI
01 Mar 1999
TL;DR: This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based system-on-chip (SOC) designs and allows concurrent hardware and software development, early verification and enables the productive re-use of intellectual property.
Abstract: This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based system-on-chip (SOC) designs. This flow, put in place within STMicroelectronics and which is called fast prototyping, allows concurrent hardware and software development, early verification and enables the productive re-use of intellectual property. We describe how using this innovative system design flow, that combines different technologies, such as C modeling, emulation, hard virtual component re-use and CoWare N2C, we achieve better productivity on a multiprocessor SOC design.

15 citations


Proceedings ArticleDOI
16 Jun 1999
TL;DR: It is shown how a formal model can be sympathetic to this type of architecture using the tool, RolEnact, and how this may be related to a COM implementation.
Abstract: Formal methods are a nice idea, but the size and complexity of real systems means that they are impractical. We propose that a reasonable alternative to attempting to specify and verify the system in its entirety is to build and evaluate an abstract model(s) of aspects of the system that are perceived as important. Using a model will not provide proof of the system, but it can help to find shortcomings and errors at an early stage. Executing the model should also give a measure of confidence in the final product. Many systems today are built from communicating components so that the task of the developers is becoming fitting these components together to form the required system. We show how a formal model can be sympathetic to this type of architecture using our tool, RolEnact and explain how this may be related to a COM implementation.

12 citations


Cites methods from "Design and use of a system-level sp..."

  • ...We show how a formal model can be sympathetic to this type of architecture using our tool, RolEnact and explain how this may be related to a COM implementation....

    [...]


References
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Journal ArticleDOI
TL;DR: It is suggested that input and output are basic primitives of programming and that parallel composition of communicating sequential processes is a fundamental program structuring method.
Abstract: This paper suggests that input and output are basic primitives of programming and that parallel composition of communicating sequential processes is a fundamental program structuring method. When combined with a development of Dijkstra's guarded command, these concepts are surprisingly versatile. Their use is illustrated by sample solutions of a variety of a familiar programming exercises.

11,284 citations


Book
01 Jan 1985

9,203 citations



Proceedings ArticleDOI
01 Dec 1995
TL;DR: This paper describes how the strengths of that system have been developed to create a VHDL simulator under UNIX while maintaining a performance level that significantly exceeds the leading commercial V HDL simulators.
Abstract: The requirements of large system design place great demands upon the performance and diagnostic capabilities of simulation. This paper explains how these requirements have been satisfied by an internally-developed simulator using a proprietary language and a proprietary platform. More significantly, this paper describes how the strengths of that system have been developed to create a VHDL simulator under UNIX while maintaining a performance level that significantly exceeds the leading commercial VHDL simulators.

3 citations


Journal Article

2 citations


"Design and use of a system-level sp..." refers background in this paper

  • ...One way to compress and effectively manage the complete product timescale is to formally capture the design earlier in the design cycle so that it can be verified earlier, and problems conforming to the requirement specification solved before reaching the later phases of the design cycle....

    [...]