Design and Verification of AMBA AXI3 Protocol
01 Jan 2018-pp 247-259
TL;DR: High percentage of bus utilization ensures that the SOC on chip bus is functioning well and makes this protocol as one of the widely used protocols in today’s SOC implementation.
Abstract: Objective: In this paper, the design and verification of AMBA AXI3 protocol are carried out in a coverage mode analysis using Verilog HDL language. Method: The design of AXI protocol is made according to its architecture specifications, and its functionality is verified using QuestaSim tool. In the AXI protocol analysis, the burst-based transactions, i.e. writing and reading of increment burst have been implemented. Findings: In addition to that the AMBA AXI efficiency is evaluated by calculating performance metrics bus utilization, busy count and valid count. In the entire paper, a verification environment is created for the verification of AXI protocol as a verification IP for modern SOC architectures. Applications: High percentage of bus utilization ensures that the SOC on chip bus is functioning well and makes this protocol as one of the widely used protocols in today’s SOC implementation.
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25 Jul 2005
TL;DR: The paper aims at surveying the evolution of the field, moving from SoC buses to forward-looking NoC research prototypes, in an effort to extract general guiding principles in a fast-evolving domain.
Abstract: Performance and power of gigascale systems-on-chip (SoCs) is increasingly communication-dominated. Designers have to accommodate the communication needs of an increasing number of integrated cores while preserving overall system performance under tight power budgets. State-of-the-art SoC communication architectures start facing scalability as well as modularity limitations, and more advanced bus specifications are emerging to deal with these issues at the expense of silicon area and complexity. Communication architecture evolutions mainly regard bus protocols (to better exploit available bandwidth) and bus topologies (to increase bandwidth). In the long run, more aggressive solutions are needed to overcome the scalability limitation, and networks-on-chip (NoCs) are currently viewed as a 'revolutionary' approach to provide a scalable, high performance and robust infrastructure for on-chip communication. The paper aims at surveying the evolution of the field, moving from SoC buses to forward-looking NoC research prototypes. The elements of continuity, as well as the key differences, will be captured, in an effort to extract general guiding principles in a fast-evolving domain.
144 citations
TL;DR: Experiments with example systems indicate that performance metrics for systems with CAT-based communication architectures are significantly better than those with conventional communication architectures.
Abstract: In this paper, we present a methodology for the design of high-performance system-on-chip communication architectures. The approach is based on the addition of a layer of circuitry called the communication architecture tuner (CAT) layer around an existing communication architecture topology. The added layer provides a system with the capability of adapting to runtime variability in the communication needs of its constituent components. For example, more critical data may be handled differently, leading to lower communication latencies. The CAT associated with each component monitors its internal state, analyzes the communication transactions it generates, and "predicts" the relative importance of the transactions in terms of their impact on system-level performance metrics. It then configures the protocol parameters of the underlying communication architecture (e.g., priorities, burst modes, etc.) to best suit the system's changing communication needs. We illustrate the issues and tradeoffs involved in the design of CAT-based communication architectures, and present algorithms that automate the key steps. Experiments with example systems indicate that performance metrics (e.g., number of missed deadlines, average processing time) for systems with CAT-based communication architectures are significantly (sometimes over an order of magnitude) better than those with conventional communication architectures.
40 citations
01 Dec 2011
TL;DR: This paper presents a project aimed to do data transactions on SoC bus using AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown inVerilog compiler simulator (VCS) tool.
Abstract: Advanced microcontroller bus architecture (AMBA) protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs The AMBA advanced extensible interface 4 (AXI4) update to AMBA AXI3 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI4 also includes information on the interoperability of components AMBA AXI4 protocol system supports 16 masters and 16 slaves interfacing This paper presents a project aimed to do data transactions on SoC bus using AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown in Verilog compiler simulator (VCS) tool The operating frequency is set to 100MHz Two test cases are run to perform multiple read and multiple write operations To perform single read operation module takes 160ns and for single write operation it takes 565ns
20 citations
13 Jun 2010
TL;DR: The evolution of NoC is considered alongside the evolution of the AMBA on-chip communication architecture, and consideration is given to the techniques that are considered most important.
Abstract: In this paper, we describe “The Evolution of SOC Interconnect and How NOC Fits Within It” which is being presented during the “A Decade of NOC Research — Where Do We Stand?” session at DAC 2010. The presentation looks at the features that have helped shape the development of on-chip interconnect solutions. The evolution of NoC is considered alongside the evolution of the AMBA on-chip communication architecture, and consideration is given to the techniques that are considered most important.
18 citations
TL;DR: A Performance Analysis Unit (PAU) is designed for monitoring the AMBA Advanced eXtensible Interface (AXI) bus as a mechanism to investigate the internal and dynamic behavior of an SOC, especially for internal bus activities.
18 citations