Design Considerations for Filtering Delta Sigma Converters
01 Jan 2017-pp 65-88
TL;DR: This work reviews filtering \(\varDelta \varSigma\) conversion and circuit techniques for Continuous-time modulators, andedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area.
Abstract: Many signal chains need to digitize signals in the presence of interferers. The usual way of accomplishing this is to use an analog anti-alias filter followed by a Nyquist ADC. Continuous-time \(\varDelta \varSigma\) modulators (CT\(\varDelta \varSigma\) M) are compelling alternatives to Nyquist rate ADCs. While oversampling relaxes the requirements of the anti-alias filter, it is natural to wonder if the built-in filtering of a CT\(\varDelta \varSigma\) M, characterized by its Signal Transfer Function (STF), can be used to attenuate interferers so that an explicit filter up front can be dispensed with altogether. It turns out that the Signal Transfer Function (STF) of a conventional CTΔ ΣM is a by-product of NTF synthesis, with the designer having little control over it. The STF can be independently controlled by using a filter up front—however, this increases power dissipation and degrades linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. This work reviews filtering \(\varDelta \varSigma\) conversion and circuit techniques for such converters.
Citations
More filters
Journal Article•
TL;DR: Finite-impulse response filters in the feedback path of a low-pass sigma-delta modulator allow a continuous-time single-bit modulator to achieve the jitter performance of a comparable multibit modulator.
Abstract: This paper explores the use of finite-impulse response (FIR) filters in the feedback path of a low-pass sigma-delta modulator in order to combat some nonideal effects encountered in an analog implementation. In this approach, the filter corresponding to the first integrator is a lowpass filter which smoothes out the feedback waveform by attenuating the high-frequency quantization noise. This lowpass filtering decreases the power consumption of a switched-capacitor implementation and alternatively reduces the sensitivity to clock jitter in a continuous-time structure. A design methodology ensuring the stability of the system is presented. Theoretical analysis and simulations show that the FIR filters allow a continuous-time single-bit modulator to achieve the jitter performance of a comparable multibit modulator.
2 citations
01 Dec 2018
TL;DR: The combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity is proposed, which is crucial to meet the strict linearity and Signal- to-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers.
Abstract: This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.
Cites background from "Design Considerations for Filtering..."
...The performance of the main feedback DAC in CTDSMs can be a limiting factor in the overall modulator’s accuracy, since any error introduced by this block appears directly at the output [3]....
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References
More filters
TL;DR: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS and the degradation of modulator stability due to excess loop delay is avoided with a new architecture.
Abstract: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply
314 citations
Proceedings Article•
01 Jan 2006
TL;DR: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation.
Abstract: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is imple- mented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time mod- ulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive contin- uous-time ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The ADC achieves 76-dB SNR, 78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply. Index Terms—Analog-to-digital conversion, CMOS analog inte- grated circuits, continuous-time modulation, continuous-time filters, delta-sigma modulation, low-pass filter, low power design, low-voltage design, multibit internal quantization, sigma-delta modulation.
232 citations
"Design Considerations for Filtering..." refers background in this paper
...Several high performance † modulators with signal bandwidths of several 10’s of MHz (keeping communication applications in mind) and about 11-12 bit resolution have been reported recently [1–3]....
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...3c) [3, 4]....
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23 Sep 2011
TL;DR: This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal 4-bit quantizer, which achieves a figure of merit of 138 fJ/conv and is used to compensate for excess loop delay.
Abstract: This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not corrected within the ΔΣ modulator loop but in the subsequent digital circuit. The unit element mismatches are digitally estimated based on a correlation, and correction factors are thus derived. Moreover, in order to achieve a low-power operation, all amplifiers are compensated for finite gain-bandwidth related non-idealities. In the presented work, this compensation includes the fast proportional loop, which is used to compensate for excess loop delay. The presented ΔΣ modulator has been realized in a 1.2 V, 90 nm CMOS process and achieves an SNDR of 63.5 dB and an SFDR of 81 dB within a 25 MHz bandwidth. The modulator occupies an active die area of only 0.15 mm2 and has a power consumption of 8 mW, with an additional 0.02 mm2 and 0.42 mW estimated for the digital DAC correction logic. The overall modulator achieves a figure of merit of 138 fJ/conv.
102 citations
"Design Considerations for Filtering..." refers background in this paper
...Several high performance † modulators with signal bandwidths of several 10’s of MHz (keeping communication applications in mind) and about 11-12 bit resolution have been reported recently [1–3]....
[...]
TL;DR: This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC, which becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel.
Abstract: Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional /spl Sigma//spl Delta/ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm/sup 2/ in a 0.18-/spl mu/m digital CMOS technology.
101 citations
TL;DR: In this article, the authors explored the use of finite-impulse response (FIR) filters in the feedback path of a low-pass sigma-delta modulator in order to combat some nonideal effects encountered in an analog implementation.
Abstract: This paper explores the use of finite-impulse response (FIR) filters in the feedback path of a low-pass sigma-delta modulator in order to combat some nonideal effects encountered in an analog implementation. In this approach, the filter corresponding to the first integrator is a lowpass filter which smoothes out the feedback waveform by attenuating the high-frequency quantization noise. This lowpass filtering decreases the power consumption of a switched-capacitor implementation and alternatively reduces the sensitivity to clock jitter in a continuous-time structure. A design methodology ensuring the stability of the system is presented. Theoretical analysis and simulations show that the FIR filters allow a continuous-time single-bit modulator to achieve the jitter performance of a comparable multibit modulator.
96 citations