Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives
05 Oct 2020-pp 198-199
TL;DR: An application of designed TRNG and PUF is proposed for implementing an authenticated key agreement protocol and efficient FPGA implementation are proposed along with relevant security analysis using prevalent metrics.
Abstract: Hardware-based security primitives play important roles in protecting and securing a system in Internet of Things (IoT) applications. The main primitives are physical unclonable functions (PUF) and true random number generator (TRNG) studied in this paper. Efficient FPGA implementation are proposed in the work along with relevant security analysis using prevalent metrics. Finally, an application of designed TRNG and PUF is proposed for implementing an authenticated key agreement protocol,
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TL;DR: An extensive survey on the current state-of-the-art of FPGA based Physically Unclonable Functions, and a detailed performance evaluation result for several FGPA based PUF designs and their comparisons are provided.
19 citations
TL;DR: In this paper , the authors present the results of different tests to demonstrate the robustness and health of the TRNG based on frequency collapse, which is used in many applications, generally for generating random cryptography keys.
Abstract: True Random Number Generator (TRNG) is used in many applications, generally for generating random cryptography keys. In this way, the trust of the cryptography system depends on the quality of the random numbers generated. However, the entropy fluctuations produced by external perturbations generate some false positives in the random sequence. These false positives can generate a disastrous scenario, depending on the application. This work presents the results of different tests to demonstrate the robustness and health of the TRNG based on frequency collapse. The TRNG passed all entropy tests provided for NIST SP800-90B and AIS31. The entropy test denotes a 0.9789 minimum normalized entropy and 7.998 Shannon entropy. In addition, the TRNG passes the health tests provided for NIST SP800-90B. The health test shows a number of identical values $I_{v}=0\%$ , $I_{v-1} < 0.004\%$ and a maximum cutoff value $MC_{v}=10$ with $LMC_{v}=13$ in the repetition count and adaptive proportion tests, respectively. The implementation passed all the statistical tests provided for NIST SP800-22 and AIS20. Besides, the implementation passes the different tests with Process, Voltage, and Temperature (PVT) variations. The TRNG is implemented in a $0.18~\mu m$ General Purpose (GP) CMOS technology, occupying $25600~\mu m^{2}$ with four entropy sources. Finally, the implementation presents a 7.3 until 9.2-Mb/s of bit rate, 0.56 until 1.88-mW of power consumption, and 77.2 until 204.3-pJ/bit of energy per bit using an entropy source with 16 and 2 delay stages, respectively.
2 citations
References
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TL;DR: This brief presents a new and efficient method to generate true random numbers on field programmable gate array (FPGA) by utilizing the random jitter of free-running oscillators as a source of randomness.
Abstract: True random number generators (TRNGs) play a fundamental role in cryptographic systems. This brief presents a new and efficient method to generate true random numbers on field programmable gate array (FPGA) by utilizing the random jitter of free-running oscillators as a source of randomness. The free-running oscillator rings incorporate programmable delay lines (PDLs) to generate large variation of the oscillations and to introduce jitter in the generated ring oscillators clocks. The main advantage of the proposed TRNG utilizing PDLs is to reduce correlation between several equal length oscillator rings, and thus improve the randomness qualities. In addition, a Von Neumann corrector as post-processor is employed to remove any bias in the output bit sequence. The validation of the proposed approach is demonstrated on Xilinx Spartan-3A FPGAs. The proposed TRNG occupies 528 slices, achieves 6 Mb/s throughput with 0.999 per bit entropy rate, and passes all the national institute of standards and technology (NIST) statistical tests.
66 citations
01 Jan 2017
TL;DR: The proposed schemes provide very competitive area trade-offs and effectively enable smallest FPGA implementations, reported so far, of RS-LPUF, RO- PUF, and A-PUF respectively.
Abstract: The Physically Unclonable Functions (PUFs) are used in numerous security applications such as device authentication, secret key generation, FPGA intellectual property (IP) protection, and trusted computing. In this paper, compact implementations of Ring oscillator-based PUF (RO-PUF), Arbiter-based PUF (A-PUF) and RS Latch-based PUF (RS-LPUF) on an FPGA (Field Programmable Gate Array) platform are presented. The proposed schemes provide very competitive area trade-offs and effectively enable smallest FPGA implementations, reported so far, of RS-LPUF, RO-PUF, and A-PUF respectively. The designs have been validated by developing prototypes on Xilinx Spartan-6 FPGAs at core voltage of 1.2V and normal operating temperature. Finally, a detailed comparison of statistical analysis on their performance using measured PUF data have been carried out. It has been demonstrated that the proposed designs exhibit significantly improved performance in terms of statistical properties when compared to the existing works.
25 citations
Additional excerpts
...In summary, the major contributions of this work are as follows: First, we have developed three major types of area efficient PUF designs and improving their qualities [2]....
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TL;DR: The implementation results show that the proposed architecture is resistant against SPA attack and yields a better performance when compared to the existing state-of-the-art BEC designs for computing point multiplication (PM).
Abstract: In this article, we present a high-performance hardware architecture for Elliptic curve based (authenticated) key agreement protocol “Elliptic Curve Menezes, Qu and Vanstone” (ECMQV) over Binary Edwards Curve (BEC). We begin by analyzing inversion module on a 251-bit binary field. Subsequently, we present Field Programmable Gate Array (FPGA) implementations of the unified formula for computing elliptic curve point addition on BEC in affine and projective coordinates and investigate the relative performance of these two coordinates. Then, we implement the w-coordinate based differential addition formulae suitable for usage in Montgomery ladder. Next, we present a novel hardware architecture of BEC point multiplication using mixed w-coordinates of the Montgomery laddering algorithm and analyze it in terms of resistance to Simple Power Analysis (SPA) attack. In order to improve the performance, the architecture utilizes registers efficiently and uses efficient scheduling mechanisms for the BEC arithmetic implementations. Our implementation results show that the proposed architecture is resistant against SPA attack and yields a better performance when compared to the existing state-of-the-art BEC designs for computing point multiplication (PM). Finally, we present an FPGA design of ECMQV key agreement protocol using BEC defined over GF(2251). The execution of ECMQV protocol takes 66.47μs using 32,479 slices on Virtex-4 FPGA and 52.34μs using 15,988 slices on Virtex-5 FPGA. To the best of our knowledge, this is the first FPGA design of the ECMQV protocol using BEC.
16 citations
TL;DR: This paper presents an area efficient hybrid PUF design on field-programmable gate array (FPGA) that combines units of conventional RS Latch-based PUF and Arbiter- based PUF which is then augmented by the programmable delay lines (PDLs) and Temporal Majority Voting (TMV) for performance enhancement.
16 citations