General rights
Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright
owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.
Users may download and print one copy of any publication from the public portal for the purpose of private study or research.
You may not further distribute the material or use it for any profit-making activity or commercial gain
You may freely distribute the URL identifying the publication in the public portal
If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately
and investigate your claim.
Downloaded from orbit.dtu.dk on: Aug 10, 2022
Design of a 300-Watt Isolated Power Supply with Minimized Circuit Input-to-Output
Parasitic Capacitance
Nguyen-Duy, Khiem; Petersen, Lars Press; Knott, Arnold; Thomsen, Ole Cornelius; Andersen, Michael
A. E.
Published in:
Proceedings of the 7th IET international conference on power electronics, machines and drives PEMD 2014
Link to article, DOI:
10.1049/iet-tv.50.19370
10.1049/cp.2014.0492
Publication date:
2014
Document Version
Early version, also known as pre-print
Link back to DTU Orbit
Citation (APA):
Nguyen-Duy, K., Petersen, L. P., Knott, A., Thomsen, O. C., & Andersen, M. A. E. (2014). Design of a 300-Watt
Isolated Power Supply with Minimized Circuit Input-to-Output Parasitic Capacitance. In Proceedings of the 7th
IET international conference on power electronics, machines and drives PEMD 2014 IEEE.
https://doi.org/10.1049/iet-tv.50.19370, https://doi.org/10.1049/cp.2014.0492
1
Design of a 300-Watt Isolated Power Supply with Minimized
Circuit Input-to-Output Parasitic Capacitance
Khiem Nguyen-Duy, Lars Press Petersen, Arnold Knott, Ole C. Thomsen, and Michael A. E. Andersen
Department of Electrical Engineering, Technical University of Denmark
Ørsteds Plads, building 349, 2800-Kgs. Lyngby, Denmark
Email: knduy@elektro.dtu.dk, lpet@elektro.dtu.dk, akn@elektro.dtu.dk, oct@elektro.dtu.dk, ma@elektro.dtu.dk
Keywords: Current transformers, parasitic capacitance,
switching converters, stacking, dc-dc power converters.
Abstract
This paper presents the design of a 300-Watt isolated power
supply for MOS gate driver circuit in medium and high
voltage applications. The key feature of the developed power
supply is having a very low circuit input-to-output parasitic
capacitance, thus maximizing its noise immunity. This makes
it suitable for modular stacking applications. The converter is
a voltage-controlled current source, utilizing a transformer
that has an extremely low inter-winding parasitic capacitance.
The experiments show that an overall circuit input-to-output
parasitic capacitance of 10 pF can be achieved. Design
analysis and experimental results are provided to prove the
feasibility of the converter.
1 Introduction
Research on common-mode noise mitigation has received
great attention since the introduction of electromagnetic
interference (EMI) regulations [1-8]. Among the existing
approaches, design of transformers with minimized inter-
winding parasitic capacitance and utilization of suitable
topologies is a very typical approach. In [1], an unusual
transformer winding structure and an unconventional
converter topology were proposed. The system achieved 1 pF
parasitic capacitance at its output power of 36 V, 0.2 A. Later
on, similar approaches [2]-[4] were proposed using a similar
transformer structure. Nevertheless, the reported previous
works provided neither experimental results nor elaborate
analysis of the converter’s operation.
This paper seeks to further investigate and validate the merit
of the converter topology in Fig. 1 which was firstly proposed
in [1]. A higher output power rating is aimed, which is 300 W
per module. The prototype is built in a way that minimizes the
circuit input-to-output parasitic capacitance, making it less
susceptible to noise and suitable for modular stacking. The
overall circuit input-to-output parasitic capacitance is 10-pF,
which, to the authors’ best knowledge, is the lowest of their
kind with 300 W output power rating.
i
V
A
B
L
v
1
v
()
L
it
2
v
o
V
C
2
()it
()
S
I
t
1
S
3
S
2
S
4
S
1
D
3
D
2
D
4
D
5
S
L
oad
S1
D
S2
D
S3
D
S4
D
S5
D
5
D
Fig. 1. Topology of the proposed converter.
2 System requirements
Referring to the converter in Fig. 1, the input dc supply
voltage of the converter is usually the output of a power
factor correction converter which converts a single phase 220-
V ac voltage into 400 V dc voltage. Therefore, a dc input of
400 V is chosen in the design. The output voltage is chosen to
be 60 V dc, since it allows a variety of power switch
selections which have a breakdown voltage of 100 V dc. If,
for example, higher output voltage is desired, then more than
one converter modules can be stacked in series. The output
current is designed to be 5 A maximum. This specification
means the maximum output power that is available in the
output terminals is 300 W. Furthermore, an extremely low
total circuit input-to-output parasitic capacitance of 10 pF is
aimed. All of these specifications are stated in Table 1.
Input voltage 400 V
Output voltage 60 V
Output current 5 A
Maximum output power 300 W
Circuit input-to-output capacitance 10 pF
Table 1. Design specification
3 Common mode noise paths
The common mode noise paths are shown in Fig. 2. In this
topology, the nodes that have high dv/dt are nodes A, B, X,
Y, and Z. In nodes A and B, there are changes of voltage from
i
Vr to
i
VB with respect to the primary side return. Nodes X,
Y, Z see a change of 0 V to 60 V with respect to the
2
secondary side return. These nodes are the sources of
common mode noise currents. In the developed prototype,
there are two heat-sinks used, one for each side to reduce the
capacitive coupling between the two sides. Since the drains of
switch
2
S and
4
S are switching nodes and they are both
attached to heat-sink 1, the coupling paths include
capacitances from drains of
2
S and
4
S to heat-sink 1, and
capacitance from heat-sink 1 to chassis/earth. In
implementation practice, the heat-sink can be electrically
connected to the return path (not the chassis/earth) to further
mitigate the transmission of common mode noise current. The
coupling paths in the secondary side include the capacitances
from cathode of
1S
D ,
2S
D ,
3S
D ,
4S
D and the drain of
5
S to
heat-sink 2, and capacitance from heat-sink 2 to chassis/earth.
The coupling path caused by the transformer is from the inter-
winding capacitance
int
C . It can be clearly seen that,
int
C is in
series with the other coupling capacitances, forming a loop of
common mode noise paths. Therefore, the value of
int
C determines the overall common mode noise performance.
The typical value for the other coupling capacitances but the
inter-winding capacitance falls into the range from 100 pF to
tens of micro farads [9]. If
int
C can be made much smaller
than the other coupling capacitances, then the overall circuit
input-to-output capacitance is governed by
int
C .
i
V
A
B
C
N
1
N
2
Load
int
C
Earth
52SHS
C
2
H
SE
C
1
H
SE
C
2
D
S
C
4
D
S
C
1GE
C
2GE
C
5
D
S
C
41SHS
C
21SHS
C
2
S
4
S
S2
D
S4
D
5
S
Heatsink 1 Heatsink 2
X
Y
Z
S1
D
S3
D
Fig. 2. Common mode noise paths
4 Transformer specification, configuration and
validation
The proposed transformer’s general structure is illustrated in
Fig. 3a, whereas the transformer under test’s photo is in Fig.
3b. In its winding configuration, the winding that has smaller
number of turns will be place in the geometry centre of the
core, forming a rectangular frame symmetrically around the
core. The remaining winding with most number of turns is
wounded tightly around the core. This is respectively the case
of the secondary winding and primary winding in Fig. 3. With
this structure, the two winding are separated from each other
by a reasonably high distance. Moreover, the die-electric
material between them is only the surrounding air, which has
the second lowest permittivity to vacuum. All of these
features results in an extremely low inter-winding parasitic
capacitance that the transformer possesses.
To arrive at a design procedure or guideline of making a
transformer that has a specific inter-winding parasitic capa-
(a) (b)
Fig. 3. Transformer structure: a) conceptual structure b) the transformer
under test.
-citance, it usually requires mathematic modelling and
solving, or simulation based on finite-element method. Apart
from that, the design of the transformer is a compromise of
different issues like its power losses and physical size of the
whole circuit. The transformer is often the most bulky part in
the prototype of a power electronics converter. As a result, the
size of the transformer highly affects the size of the prototype.
It is preferable to go for smaller size of transformer so that the
prototype is smaller, and therefore, the parasitic capacitance
coupling to earth is smaller. The derivation of the transformer
design procedure can be treated as a separated issue. This
issue, however, is not addressed in this paper, which focuses
on system analysis and experiment validation of the converter
as a whole.
Material N87
Dimension 36 mm×25 mm×13 mm
Turn ratio 55:11
Primary winding Litz-wire 60×0.2 mm
Secondary winding Copper 1 mm
Table 2. Transformer parameters
The specifications of the developed transformer are provided
in Table 2. Fig. 4. shows the experimental data of the inter-
winding impedance magnitude and phase of the transformer.
It is done with both terminals of each winding shorted. As can
be seen, the impedance magnitude has a constant slope with -
20dB/dec roll off, and the phase is around -90
0
. Therefore, the
inter-winding is capacitive and it is appropriate to model the
inter-winding impedance as a lump-element circuit with an
inter-winding-capacitor. The measured data are in the form of
digital values of impedance’s magnitude and phase at a sweep
of different frequencies. They are imported into MATLAB
and processed by proper scripts to yield the interpreted
coupling capacitance, whose values are shown in Fig. 5. It
can be seen that the capacitance value is around 10 pF in the
wide range of frequency from dc to 10 MHz. It is validated
that with the distinct configuration of the transformer, an
extremely low inter-winding parasitic capacitance can be
achieved.
3
The process is repeated for the measurement of the
impedance between two terminals of the primary side while
the two terminals of the secondary side shorted. This
impedance can be modelled as a leakage inductor. The
impedance magnitude and phase are shown in Figs. 6a and
6b. The impedance behaves like a resistor at frequency up to
1 kHz due to winding ohmic resistance, like a leakage
inductor from 2 kHz to 1.5 MHz due to leakage flux, and like
a capacitor from above 1.5 MHz due to the self-capacitance
of the leakage inductor. The interpreted magnitude of the
leakage inductor is shown in Fig. 6c. The leakage inductance
value is 170 uH in the range of 100 kHz to 300 kHz. The
consequential relatively high leakage inductance can be
explained as being caused by the high geometry separation of
the two windings which produces relatively large leakage flux
outside the core. Hence, the proposed topology as well as its
associated control approach should be able to utilize the
leakage inductor. The control approach will be presented in
the next section.
10
2
10
3
10
4
10
5
10
6
10
7
10
2
10
4
10
6
10
8
10
10
Frequency (Hz)
Absolute Impedance (Ohm)
Fig. 4 (a)
10
2
10
3
10
4
10
5
10
6
10
7
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Frequency (Hz)
Phase (deg)
Fig. 4(b)
Fig. 4. Inter-winding impedance measurement: a) magnitude, b) phase
10
2
10
3
10
4
10
5
10
6
10
7
10
-12
10
-11
10
-10
Frequency (Hz)
Transformer C
int
(F)
Fig. 5. Interpreted parasitic capacitance
10
2
10
3
10
4
10
5
10
6
10
7
10
0
10
1
10
2
10
3
10
4
Frequency (Hz)
Absolute Impedance (Ohm)
(a)
10
2
10
3
10
4
10
5
10
6
10
7
-80
-60
-40
-20
0
20
40
60
80
Frequency (Hz)
Phase (deg)
(b)
10
2
10
3
10
4
10
5
10
6
10
7
10
-7
10
-6
10
-5
10
-4
10
-3
Frequency (Hz)
Leakage Inductance (H)
(c)
Fig. 6. Primary winding impedance: a) magnitude, b) phase, c) interpreted
leakage inductance
5 Converter operation and control
In this paper, the control approach without an isolated
feedback is adopted as to achieve minimum circuit input-to-
output parasitic capacitance. The proposed physical con-
figuration of the converter is shown in Fig. 7. There are two
control loops where one resides in the primary and the other
one resides in the secondary. The secondary side controller
regulates the output voltage to be constant at 60 V. The
primary side controller controls the primary-side inductor
current; thus, indirectly regulate the nominal output current.
The secondary side circuit can be seen as a current source
supplying the output capacitor in parallel with the load.
Because of the diode rectification in the secondary side, the
output current is the result of the rectified inductor current
multiplying with the inversion of the turn ratio.
1
2
() ()
SL
N
I
tit
N
(1)
The secondary side controller regulates the output voltage to
be constant at 60 V. The output voltage is sensed by a voltage
divider, compared to a hysteresis reference to switch on and
off the shunt switch S
5
. When switch S
5
is on, shunting the
4
N
1
N
2
H-Bridge
Shunt
Regulator
Feedback &
Self-supply
Feedback
Controller
Drivers
Output
Input
Auxi-
liary
+15V
+15V
400V
60V
Isolation
Boundary
Driver
Controller
Current
Sensor
Fig. 7. Block diagram of the physical layout of the converter
i
V
A
B
1
v
2
v
o
V
C
2
()it
()
L
it
(a)
()
S
It
i
V
A
B
()
L
it
o
V
C
2
()it
1
v
2
v
(b)
Fig. 8. Operation modes: a) shunt mode, b) power mode.
()
AB
vt
()
L
it
()
S
It
()
S
It
2
()vt
1i
VV
1i
VV
1i
VV
1i
VV
i
V
i
V
1
T
2
T
()Bt
max
B
min
B
()Bt
()
L
vt
1, 4PWM S
2,3PWM S
1, 4PWM S
2,3PWM S
i
V
i
V
i
V
i
V
()
L
it
o
V
()
L
vt
()
AB
vt
2
()vt
o
V
1
D
4
D
1
S
4
S
2
D
3
D
2
S
3
S
1
D
4
D
1
S
4
S
2
D
3
D
2
S
3
S
(a) (b)
Fig. 9. Analytical waveforms when converter operates in a) shunt mode, b)
power mode.
secondary side, the converter operates in its shunt mode (Figs.
8a and 9a); the output voltage decreases. Vice versa, when S
5
is off, the converter operates in its power mode, which is
shown in Figs. 8b and 9b; the output voltage increases. In the
primary side, since the leakage inductance is relatively high,
which is 170 uH; it is utilized as the main inductor in the
circuit and there is no external inductor added. The primary
side inductor current can be controlled by either adjusting one
variable among the three variables of the primary switches:
frequency, phase shift, or duty cycle. In this paper, the
frequency modulation is chosen. The duty cycle of the
switches is kept at 50%, and the phase-shift is therefore at
zero degree. The primary side current i
L
is sensed and
rectified. After that, it is low-pass filtered (LPF) to get the
rectified-dc value. This value is then compared to a rectified-
dc reference and processed by an analogue proportional-
integral (PI) compensator. The output of the PI compensator
is fed to a voltage-controlled oscillator (VCO) to keep the
rectified primary dc current to be constant at 1 A dc. With a
turn ratio of 5:1, the rectified dc current at the secondary side
is controlled at 5 A dc. The control block diagrams are
presented in Fig. 10.
The switching frequency that ensure the primary side to be
regulated at the peak value of
l
L
i can be derived by equating
the product of voltage across the inductor and time when the
current is negative to the one during which the current is
positive. It can be proved that:
l
2
1
2
1
4
i
i
L
V
V
f
V
iL
§·
¨¸
©¹
(2)
In the power mode, the voltage across the primary winding of
the transformer
1
V is reflected from the output voltage from
the secondary side multiplied by the turn ratio if forward
voltage drops from the rectifier stage diodes are neglected. In
the shunt mode, this voltage becomes zero. As a result, the
two switching frequencies at power mode and shunt mode
are:
l
2
20 1
2
(/)
1
4
i
power
i
L
VNVN
f
V
iL
§·
¨¸
©¹
(3)
l
4
i
shunt
L
V
f
iL
(4)
oref
V
()
o
Vt
5
S
()V
5
S
H
H
(a)
L
dc
i
L
ref
I
abs
LPF
()
L
it
pi
kkdt
³
VCO
(b)
Fig. 10. Control block diagram: a) hysteresis control in the secondary side b)
average current control in the primary side
