Design of a High Performance Reversible Multiplier
01 Jan 2011-
TL;DR: The proposed 4×4 reversible multiplier circuit has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and number of garbage outputs with compared to the existing counterparts.
Abstract: Reversible logic circuits are increasingly used in power minimization having applications such as low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. In this paper we propose a new 4×4 universal reversible logic gate. The proposed reversible gate can be used to synthesize any given Boolean functions. The proposed reversible gate also can be used as a full adder circuit. In this paper we have used Peres gate and the proposed Modified HNG (MHNG) gate to construct the reversible fault tolerant multiplier circuit. We show that the proposed 4×4 reversible multiplier circuit has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and number of garbage outputs with compared to the existing counterparts.
Citations
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TL;DR: This paper portrays the designing of Reversible Logic gates through the use of Quantum Dot Cellular Automata (QCA) which is a nanotechnology concept and also a striking substitute for transistor based technologies.
Abstract: This paper portrays the designing of Reversible Logic gates through the use of Quantum Dot Cellular Automata (QCA) which is a nanotechnology concept and also a striking substitute for transistor based technologies. This technology helps us to rise above the confines of CMOS technology. It also gives better results in terms of digital and analog waveform, Quantum cost, garbage output. The fundamental logic in QCA is the logic state that does not compute with voltage level; rather it measures the polarity of electrons in a quantum cell. Basically Reversible logic gates are an essential building block of various computing system. Comparing with standard gates, the reversible logic gate lower the information bits use loss by reusing the logic information bits logically and realizes the goal of lowering power consumption of logic circuits. A QCAdesigner tool is used for simulation of different kinds of Reversible logic gates such as Toffoli gate, Fredkin gate and some others.
11 citations
Cites background from "Design of a High Performance Revers..."
...It has same number of input and output lines whereas the output line which was not utilize in any circuit was considered to be a garbage signal and the fan-out of each output line is one [2]....
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09 Jan 2014
TL;DR: In this article, the authors presented and implemented reversible Wallace signed multiplier circuit in ASIC through modified Baugh-Wooley approach using standard reversible logic gates/cells, based on complementary pass-transistor logic and have been validated with simulations, a layout vs. Schematic check, and a design rule check.
Abstract: Reversible logic is very much in demand for the future computing technologies as they are known to produce low power dissipation having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Adders and multipliers are fundamental building blocks in many computational units. In this paper we have presented and implemented reversible Wallace signed multiplier circuit in ASIC through modified Baugh-Wooley approach using standard reversible logic gates/cells, based on complementary pass-transistor logic and have been validated with simulations, a layout vs. Schematic check, and a design rule check. It is proved that the proposed multiplier is better and optimized, compared to its existing counterparts with respect to the number of gates, constant inputs, garbage outputs, hardware complexity, and number of transistors required. It has also been shown in Cadence's tools that the reversible multiplier outperform the irreversible multiplier in terms of power dissipation.
11 citations
TL;DR: New designs of a reversible carry-look-ahead adder with better performance compared to the existing designs are presented, then using 2’s complement method, a reversible Carry/borrow look- Ahead adder/subtractor is designed.
Abstract: Reversible logic has received great attention in recent years due to its ability to reduce power consumption. Reversible logic improves energy efficiency, velocity of nano-circuits and the portability. We can construct irreversible circuits using reversible gates. Adders are one of the most important elements of digital circuits. Among all different types of adders, carry-look-ahead adder is the fastest. This paper presents new designs of a reversible carry-look-ahead adder with better performance compared to the existing designs, then using 2’s complement method, a reversible carry/borrow look-ahead adder/subtractor is designed. The proposed designs are simulated by VHDL, and the results are compared to the existing designs.
8 citations
01 Dec 2015
TL;DR: A new reversible gate of 4×4 size named as CSMT gate is proposed to design an optimized binary to gray code converter and the proposed design of the converter is optimized as compared to the existing designs.
Abstract: Technological innovations of this era demand the application of reversible logic approach to design various low power loss digital systems. Reversible designs are widely applicable in the area of quantum computing, low power CMOS designs, optical computing, bioinformatics etc. This technique of digital circuit designing aims to produce ideally zero power loss electronic devices. In this paper, we have proposed a new reversible gate of 4×4 size named as CSMT gate. Here, the application of CSMT gate is limited to design an optimized binary to gray code converter. The proposed design of the converter is optimized as compared to the existing designs. The optimization of the designs are compared on some selected performance parameters such as reversible gates used, garbage output generated, constant input signals applied and quantum cost of the digital circuit.
6 citations
TL;DR: A brief review on evolution of the QCA in reversible computing is discussed, and various reversible gates that are designed using QCA technology as well as the modification of those designs that are made in latter works are highlighted.
Abstract: Abstract Shrinking transistor sizes and power dissipation are the major barriers in the development of future computational circuits. At least when the transistor size approaches the atomic scale, duplication of transistor density according to Moore’s law will not be possible. Physical limits, like quantum effects and nondeterministic behavior of small currents, and technological limits, such as high power consumption and design complexity, may hold back the future program of microelectronic conventional circuit scaling. Hence, an alternative technology is required for future design. Quantum dot-cellular automata (QCA) is a transistor-less, very promising nanotechnology that can be used to build nanocircuits. The conventional computer is an irreversible one; i.e. once a logic block generates the output bits, the input bits are lost. A possible solution is reversible computing, where no bit is lost during computation. Hence, logically reversible circuit can consume less energy than any conventional circuit. In this paper, a brief review on evolution of the QCA in reversible computing is discussed. Various reversible gates that are designed using QCA technology as well as the modification of those designs that are made in latter works are highlighted.
6 citations
References
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TL;DR: Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
Abstract: It is argued that computing machines inevitably involve devices which perform logical functions that do not have a single-valued inverse. This logical irreversibility is associated with physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function. This dissipation serves the purpose of standardizing signals and making them independent of their exact logical history. Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
3,629 citations
"Design of a High Performance Revers..." refers background in this paper
...3806505x10 23 m(2) kg k -1 (joules Kelvin (1)) is the Boltzman constant and T is the operating temperature [1]....
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...Landauer in the early 1960s, irreversible hardware computation, regardless of its realization technique, results in energy dissipation due to the information loss[1]....
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IBM1
TL;DR: This result makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step.
Abstract: The usual general-purpose computing automaton (e.g.. a Turing machine) is logically irreversible- its transition function lacks a single-valued inverse. Here it is shown that such machines may he made logically reversible at every step, while retainillg their simplicity and their ability to do general computations. This result is of great physical interest because it makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step. In the first stage of its computation the logically reversible automaton parallels the corresponding irreversible automaton, except that it saves all intermediate results, there by avoiding the irreversible operation of erasure. The second stage consists of printing out the desired output. The third stage then reversibly disposes of all the undesired intermediate results by retracing the steps of the first stage in backward order (a process which is only possible because the first stage has been carried out reversibly), there by restoring the machine (except for the now-written output tape) to its original condition. The final machine configuration thus contains the desired output and a reconstructed copy of the input, but no other undesired data. The foregoing results are demonstrated explicitly using a type of three-tape Turing machine. The biosynthesis of messenger RNA is discussed as a physical example of reversible computation.
3,497 citations
Book•
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01 Jan 2001
TL;DR: Conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation and proves that universal computing capabilities are compatible with the reversibility and conservation constraints.
Abstract: Conservative logic is a comprehensive model of computation which explicitly reflects a number of fundamental principles of physics, such as the reversibility of the dynamical laws and the conservation of certain additive quantities (among which energy plays a distinguished role). Because it more closely mirrors physics than traditional models of computation, conservative logic is in a better position to provide indications concerning the realization of high-performance computing systems, i.e., of systems that make very efficient use of the "computing resources" actually offered by nature. In particular, conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation. After establishing a general framework, we discuss two specific models of computation. The first uses binary variables and is the conservative-logic counterpart of switching theory; this model proves that universal computing capabilities are compatible with the reversibility and conservation constraints. The second model, which is a refinement of the first, constitutes a substantial breakthrough in establishing a correspondence between computation and physics. In fact, this model is based on elastic collisions of identical "balls" and thus is formally identical with the atomic model that underlies the (classical) kinetic theory of perfect gases. Quite literally, the functional behavior of a general-purpose digital computer can be reproduced by a perfect gas placed in a suitably shaped container and given appropriate initial conditions.
1,888 citations
"Design of a High Performance Revers..." refers background in this paper
...Some of them are: Feynman gate, FG [6], Toffoli gate, TG [7], Fredkin gate, FRG[15], Peres gate, PG [11], New Gate, NG [14], TSG gate, TSG [5], MKG gate, MKG [16] and HNG gate, HNG [18]....
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TL;DR: The physical limitations due to quantum mechanics on the functioning of computers are analyzed in this paper, where the physical limitations of quantum mechanics are discussed and the physical limits of quantum computing are analyzed.
Abstract: The physical limitations, due to quantum mechanics, on the functioning of computers are analyzed.
1,717 citations
Proceedings Article•
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14 Jul 1980
TL;DR: According to a physical interpretation, the central result of this paper is that i¢ is ideally possible to build sequential c/rcuits with zero internal power dissipation.
Abstract: The theory of reversible computing is based on invertib|e primitives and composition rules that preserve invertibility. With these constraints, one can still satisfactorily deal with both functional and structural aspects of computing processes; at the same time, one attains a closer correspondence between the behavior of abstract computing systems and the microscopic physical laws (which are presumed to be strictly reversible) that underly any concrete implementation of such systems. According to a physical interpretation, the central result of this paper is that i¢ is ideally possible to build sequential c/rcuits with zero internal power dissipation.
1,357 citations
"Design of a High Performance Revers..." refers background in this paper
...Some of them are: Feynman gate, FG [6], Toffoli gate, TG [7], Fredkin gate, FRG[15], Peres gate, PG [11], New Gate, NG [14], TSG gate, TSG [5], MKG gate, MKG [16] and HNG gate, HNG [18]....
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