Design of a low power 4×4 multiplier based on five transistor (5-T) half adder, eight transistor (8-T) full adder & two transistor (2-T) AND gate
16 Mar 2015-pp 1-5
TL;DR: Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier, which achieves a high speed low power design for the multiplier.
Abstract: In this paper, we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.
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23 Mar 2019
TL;DR: This paper represents a new design of a low power, low latency Wallace tree multiplier that has the best power and delay results as compared to other available multipliers.
Abstract: This paper represents a new design of a low power, low latency Wallace tree multiplier. Wallace Tree algorithm is one of the most commonly used operations in modern days DSP applications as it can provide a fast and area efficient strategy for higher operand multiplication. For higher bits of multiplications the addition operation of partial products includes greater delay and complexity. In this present communication a number of techniques are applied in the partial products addition circuitry to optimize the area delay and speed of the Wallace multiplier. Proposed Design is synthesized for $4\mathrm{x}4$ bit multiplication using standard CAD tool design compiler in 250nm process technology. Simulation results show that the proposed multiplier design has the best power and delay results as compared to other available multipliers.
11 citations
Cites methods from "Design of a low power 4×4 multiplie..."
...Figure 3 shows transistorized schematic of a partial product generator using GDI MUX based AND gate [2]....
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...In the proposed design half adders are implemented using a 3T XOR and 2T GDI MUX [2]....
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...In the proposed design half adders are implemented using a 3T XOR and 2T GDI MUX [2]....
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...Figure 3 shows transistorized schematic of a partial product generator using GDI MUX based AND gate [2]....
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...In the proposed design full adders have been implemented using two nos. of 3T XOR gates and a GDI MUX....
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TL;DR: A low-power, high-speed 4×4 multiplier using Dadda algorithm is proposed, designed using reduced-split precharge-data driven dynamic sum logic and implemented in 1P-9M Low-K UMC 90nm CMOS process technology.
Abstract: A low-power, high-speed $$4\times 4$$4×4 multiplier using Dadda algorithm is proposed. The full adder blocks used in this multiplier have been designed using reduced-split precharge-data driven dynamic sum logic. Flip flops used in the pipeline registers have been designed to increase input signal noise margin, resulting in the minimization of output signal glitches. The multiplier circuit is implemented in 1P-9M Low-K UMC 90nm CMOS process technology. Post-layout simulations are carried out using Cadence Virtuoso. The proposed multiplier operates at a clock frequency of 3.5 GHz, with an average dynamic power consumption of 1.096 mW at a temperature of $$27\,^{\circ }\hbox {C}$$27źC and 1 V supply voltage and occupies a chip area of $$76\,\upmu \hbox {m}\times 102\,\upmu \hbox {m}$$76μm×102μm.
9 citations
Additional excerpts
...Se ling Time (ns) Proposed [13] [11] [4] [2] [15] 0 1 2 3 4 5...
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...Dynamic Power (μW) Proposed [13] [11] [4] [2] [15] 0 200 400 600 800 1000 1200...
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01 Nov 2018
TL;DR: A low power GDI based radix-4 modified Booth-Wallace multiplier has been projected and CAD tool based simulation shows 35% reduction in power consumption compared to other existing designs.
Abstract: In modern trend, as we are moving for niche devices power managing is a serious anxiety for all handy electronic gadgets. The performance of the device depends highly on temperature profile, which changes rapidly with high power consumption. As most of the devices run by the digital signal processor, the power consumption of DSP chip is the main concern. In the majority of the signal processing algorithms, multiplication operation dominates other operations. Hence in modern low power VLSI design one of the major challenges is to design an efficient multiplier block. In this paper, a low power GDI based radix-4 modified Booth-Wallace multiplier has been projected. CAD tool based simulation shows 35% reduction in power consumption compared to other existing designs.
6 citations
Cites background from "Design of a low power 4×4 multiplie..."
...The actual result is 2N bits wide for an NxN multiplier, generated by getting the added value of all the corresponding products [16]....
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TL;DR: The proposed low-precision SFTQ quantization (SFTQ) scheme provides significant imaging quality improvements, especially when the quantization level is low, and its advantage in computational complexity is also analyzed.
Abstract: It has been proven that the imaging quality of 1-bit quantized synthetic aperture radar (SAR) data can be improved by using an imaging scheme of a single-frequency threshold (SFT) In this article, such a quantization model is specialized to a fixed threshold application by setting the frequency of the threshold to zero Using multiple fixed thresholds, the conventional quantization schemes are also assimilated into this model In this way, the performance degradation caused by low-precision quantization is analyzed in terms of harmonics, and the SFT quantization (SFTQ) strategy is addressed to handle the issue of performance degradation The proposed quantization scheme provides significant imaging quality improvements, especially when the quantization level is low, and its advantage in computational complexity is also analyzed Simulations on different SAR scenes show that the SFTQ, compared with the conventional quantizers, is able to guarantee 97% information in the SAR imagery while consuming less than 1/6 hardware for pulse compression Therefore, the proposed low-precision SFTQ is a promising approach to SAR system miniaturization
6 citations
4 citations
References
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TL;DR: In this article, a complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path, which consists of complementary inputs/outputs, an nMOS pass transistor logic network, and CMOS output inverters, and is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality.
Abstract: A 38-ns, 257-mW, 16*16-b CMOS multiplier with a supply voltage of 4 V is described A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 26 ns with 60 mW at 77 K >
485 citations
"Design of a low power 4×4 multiplie..." refers background in this paper
...Two of them, simultaneously developed by Hitachi CPL [4] and DPL [5] are the most notables....
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...Double-Pass-transistor-Logic (DPL) eliminates some of the inverter stages required for Complementary-Pass-transistorLogic (CPL) by using both N and P channel transistors, with dual logic paths for every function [3]....
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TL;DR: This paper proposes a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones to reduce the threshold-voltage loss of the pass transistors.
Abstract: Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones. We have done over 10,000 HSPICE simulation runs of all the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while three new adders consistently consume on average 10% less power and have higher speed compared with the previous 10-transistor full adder and the conventional 28-transistor CMOS adder. One draw back of the new adders is the threshold-voltage loss of the pass transistors.
306 citations
"Design of a low power 4×4 multiplie..." refers background in this paper
...Recently many techniques have been proposed with the objective of improving speed and power consumption [2]-[6]....
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01 Nov 1993
TL;DR: A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path and the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU.
Abstract: Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >
221 citations
"Design of a low power 4×4 multiplie..." refers background in this paper
...There are three major sources of power dissipation in a digital CMOS circuit: logic transition, short-circuit current and leakage current [5], [6]....
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...Two of them, simultaneously developed by Hitachi CPL [4] and DPL [5] are the most notables....
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...Double-Pass-transistor-Logic (DPL) eliminates some of the inverter stages required for Complementary-Pass-transistorLogic (CPL) by using both N and P channel transistors, with dual logic paths for every function [3]....
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...The short-circuit current is the direct current passing through the supply and the ground, when both the NMOS and the PMOS transistors are simultaneously active [5], [10]....
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TL;DR: A novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T) that has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption.
Abstract: The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.
199 citations
TL;DR: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology and a new 4-2 compressor and a carry lookahead adder (CLA) have been developed to enhance the speed performance.
Abstract: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >
179 citations