Design of an efficient vedic binary squaring circuit

TLDR: A comparative study of the projected architecture and the prevailing multipliers, on the premise of delay and space utilization is presented and the simulation outcome proves that the design projected employing Nikhilam sutra improves the performance significantly.

Abstract: High speed and less area have always been a major concern in VLSI design. With this as a constraint, in this paper a dedicated architecture which is exclusively used for squaring operation has been proposed. Squaring plays a vital role in many signal processing applications and probabilistic analysis in communication systems, where, quite often general multipliers are used although squaring has to be done. This unnecessarily increases the area of the design and also increases the computation time. The principles of Nikhilam Sutra have been leveraged and is extended for squaring binary bits. A comparative study of the projected architecture and the prevailing multipliers, on the premise of delay and space utilization is presented. The simulation outcome proves that the design projected employing Nikhilam sutra improves the performance significantly. The 8-bit architecture has been developed by Verilog HDL and the synthesis is completed using Xilinx ISE - 14.5 software.