Design Of Analog Cmos Integrated Circuits
01 Jan 2016-
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Citations
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TL;DR: In this paper, field effect transistors from single and few-layer rhenium disulfide were constructed and observed an anisotropic ratio of three to one along the two principle axes.
Abstract: Many two-dimensional materials exhibit isotropic properties, but anisotropy can extend the functionality of future devices. Here, the authors fabricate field-effect transistors from single and few-layer rhenium disulfide and observe an anisotropic ratio of three to one along the two principle axes
539 citations
TL;DR: The overall performance is numerically investigated showing that using the proposed technique, the self-interference signal could be mitigated to ~3 dB higher than the receiver noise floor, which results in up to 76% rate improvement compared to conventional half-duplex systems at 20 dBm transmit power values.
Abstract: Full-duplex systems are expected to double the spectral efficiency compared to conventional half-duplex systems if the self-interference signal can be significantly mitigated. Digital cancellation is one of the lowest complexity self-interference cancellation techniques in full-duplex systems. However, its mitigation capability is very limited, mainly due to transmitter and receiver circuit's impairments. In this paper, we propose a novel digital self-interference cancellation technique for full-duplex systems. The proposed technique is shown to significantly mitigate the self-interference signal as well as the associated transmitter and receiver impairments. In the proposed technique, an auxiliary receiver chain is used to obtain a digital-domain copy of the transmitted Radio Frequency (RF) self-interference signal. The self-interference copy is then used in the digital-domain to cancel out both the self-interference signal and the associated impairments. Furthermore, to alleviate the receiver phase noise effect, a common oscillator is shared between the auxiliary and ordinary receiver chains. A thorough analytical and numerical analysis for the effect of the transmitter and receiver impairments on the cancellation capability of the proposed technique is presented. Finally, the overall performance is numerically investigated showing that using the proposed technique, the self-interference signal could be mitigated to ~3dB higher than the receiver noise floor, which results in up to 76% rate improvement compared to conventional half-duplex systems at 20dBm transmit power values.
313 citations
Cites background from "Design Of Analog Cmos Integrated Ci..."
...In practical systems, the nonlinearity is typically characterized by the thirdorder intercept point (IP3), which is defined as the point at which the power of the third harmonic is equal to the power of the first harmonic [23]....
[...]
...The overall receiver noise figure can be written as a function of the noise figure of each individual block as [23]...
[...]
09 Mar 2015
TL;DR: Adaptive-Latency DRAM (AL-DRAM), a mechanism that adoptively reduces the timing parameters for DRAM modules based on the current operating condition, is proposed and shown that dynamically optimizing the DRAM timing parameters can reliably improve system performance.
Abstract: In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85° C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55° C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case. Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55°C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adoptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface. We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.
236 citations
Cites methods from "Design Of Analog Cmos Integrated Ci..."
...To be technology-independent, we model the DRAM circuitry using NMOS and PMOS transistors that obey the well-known MOSFET equation for current-voltage (SPICE) [56]....
[...]
TL;DR: A Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime at low supply voltages and ultralow power is reported, minimizes power consumption by operating near the off-state limit.
Abstract: The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages ( 400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.
196 citations
Cites background or result from "Design Of Analog Cmos Integrated Ci..."
...Here, Ai of the SB-TFT is at least an order of magnitude higher compared to the ohmic IGZO TFT (table S3) and a typical Si-MOSFET (17,18)....
[...]
...Here,Ai of the SB-TFT is at least an order of magnitude higher compared to the ohmic IGZO TFT (table S3) or a typical Si-MOSFET (17, 18)....
[...]
...This bias independence of intrinsic gain and zero input current by virtue of the insulated gate makes the SB-TFT, operating near the OFF-state, capture the best of the bipolar junction transistor (BJT) and metal-oxide-semiconductor field-effect transistor (MOSFET) technology families (table S4) (16-18)....
[...]
TL;DR: A high-gain, fully inkjet-printed Schottky barrier organic thin-film transistor amplifier circuit that delivered gain near the theoretical limit at a power below 1 nanowatt and detected electrophysiological signals from the skin with a wearable device is reported.
Abstract: Overcoming the trade-offs among power consumption, fabrication cost, and signal amplification has been a long-standing issue for wearable electronics. We report a high-gain, fully inkjet-printed Schottky barrier organic thin-film transistor amplifier circuit. The transistor signal amplification efficiency is 38.2 siemens per ampere, which is near the theoretical thermionic limit, with an ultralow power consumption of 60 decibels and noise voltage of <0.3 microvolt per hertz1/2 at 100 hertz.
177 citations
Additional excerpts
...Thus, the SB-OTFT could provide a high intrinsic gain (defined as Ai = gmro) (25), resulting from the high transconductance and output resistance....
[...]
References
More filters
TL;DR: In this paper, field effect transistors from single and few-layer rhenium disulfide were constructed and observed an anisotropic ratio of three to one along the two principle axes.
Abstract: Many two-dimensional materials exhibit isotropic properties, but anisotropy can extend the functionality of future devices. Here, the authors fabricate field-effect transistors from single and few-layer rhenium disulfide and observe an anisotropic ratio of three to one along the two principle axes
539 citations
TL;DR: In this paper, the authors proposed a digital self-interference cancellation technique for full-duplex systems, which is shown to significantly mitigate the selfinterference signal as well as the associated transmitter and receiver impairments, more specifically, transceiver nonlinearities and phase noise.
Abstract: Full-duplex systems are expected to double the spectral efficiency compared to conventional half-duplex systems if the self-interference signal can be significantly mitigated. Digital cancellation is one of the lowest complexity self-interference cancellation techniques in full-duplex systems. However, its mitigation capability is very limited, mainly due to transmitter and receiver circuit's impairments (e.g., phase noise, nonlinear distortion, and quantization noise). In this paper, we propose a novel digital self-interference cancellation technique for full-duplex systems. The proposed technique is shown to significantly mitigate the self-interference signal as well as the associated transmitter and receiver impairments, more specifically, transceiver nonlinearities and phase noise. In the proposed technique, an auxiliary receiver chain is used to obtain a digital-domain copy of the transmitted Radio Frequency (RF) self-interference signal. The self-interference copy is then used in the digital-domain to cancel out both the self-interference signal and the associated transmitter impairments. Furthermore, to alleviate the receiver phase noise effect, a common oscillator is shared between the auxiliary and ordinary receiver chains. A thorough analytical and numerical analysis for the effect of the transmitter and receiver impairments on the cancellation capability of the proposed technique is presented. Finally, the overall performance is numerically investigated showing that using the proposed technique, the self-interference signal could be mitigated to $\sim$ 3 dB higher than the receiver noise floor, which results in up to 76% rate improvement compared to conventional half-duplex systems at 20 dBm transmit power values.
343 citations
09 Mar 2015
TL;DR: Adaptive-Latency DRAM (AL-DRAM), a mechanism that adoptively reduces the timing parameters for DRAM modules based on the current operating condition, is proposed and shown that dynamically optimizing the DRAM timing parameters can reliably improve system performance.
Abstract: In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85° C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55° C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case. Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55°C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adoptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface. We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.
236 citations
TL;DR: A Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime at low supply voltages and ultralow power is reported, minimizes power consumption by operating near the off-state limit.
Abstract: The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages ( 400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.
196 citations
TL;DR: A high-gain, fully inkjet-printed Schottky barrier organic thin-film transistor amplifier circuit that delivered gain near the theoretical limit at a power below 1 nanowatt and detected electrophysiological signals from the skin with a wearable device is reported.
Abstract: Overcoming the trade-offs among power consumption, fabrication cost, and signal amplification has been a long-standing issue for wearable electronics. We report a high-gain, fully inkjet-printed Schottky barrier organic thin-film transistor amplifier circuit. The transistor signal amplification efficiency is 38.2 siemens per ampere, which is near the theoretical thermionic limit, with an ultralow power consumption of 60 decibels and noise voltage of <0.3 microvolt per hertz1/2 at 100 hertz.
177 citations