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Proceedings ArticleDOI

Design of band-gap engineered silicon-germanium Junctionless Double-gate FET for ZRAM application

TL;DR: In this paper, a single transistor and zero-capacitor dynamic random access memory (DRAM or ZRAM) using band-gap engineered silicon-germanium (SiGe) junctionless double gate field effect transistor (JL-DGFET) device structure through 2D Sentaurus TCAD numerical simulations was designed.
Abstract: In this paper, we design a single transistor and zero-capacitor dynamic random access memory (DRAM or ZRAM) using band-gap engineered silicon-germanium (SiGe) Junctionless Double Gate Field Effect Transistor (JL-DGFET) device structure through 2D Sentaurus TCAD numerical simulations. We see that the inadequate charge storage capability of silicon-based 1T-DRAM is the main reason for short retention time. However, our simulations show that the performance can be further improved by replacing silicon substrate with silicon-germanium material. Moreover, a reduced breakdown voltage and hysteresis I DS -V DS characteristics are observed by putting SiGe as a bulk. Furthermore, the thickness of oxide and bulk material, and doping concentration are varied and their impacts are shown on the hysteresis output characteristic. High value of bipolar gain (β) is attained in designed band-gap engineered Si (1−x) Ge x JL-DGFET transistors, which can be employed for enhancement of sensing margin in dynamic memories.
Citations
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Proceedings ArticleDOI
H. Komiya1
18 Oct 1993
TL;DR: In this paper, the authors examined the production cost and design cost of VLSI, for example, DRAMs (dynamic random access memory) and gate arrays, which have driven the progress in silicon-based-memory process technology and in ASIC (application specific integrated circuit) design technology, respectively.
Abstract: Technological trends for VLSI are discussed, with emphasis on process/device technology and function/performance forecasts. Economic trends are then examined. The production cost and design cost of VLSI are analyzed. Particular attention is given to the production cost of VLSI, for example, DRAMs (dynamic random access memory) and gate arrays, which have driven the progress in silicon-based-memory process technology and in ASIC (application-specific integrated circuit) design technology, respectively. Future production-cost trends are estimated for both. >

3 citations

References
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Journal ArticleDOI
David J. Frank1, R.H. Dennard1, E. J. Nowak1, Paul M. Solomon1, Yuan Taur1, Hon-Sum Philip Wong1 
01 Mar 2001
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

1,417 citations

Journal ArticleDOI
TL;DR: In this article, the improvement of sub-threshold slope due to impact ionization is compared between standard inversion-mode multigate silicon nanowire transistors and junctionless transistors.
Abstract: The improvement of subthreshold slope due to impact ionization is compared between “standard” inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope.

220 citations


"Design of band-gap engineered silic..." refers background in this paper

  • ...The continuous downscaling trend for performance advancement of conventional metal oxide semiconductor field effect transistor (MOSFET) is limited by short channel effects (SCEs) such as: sub-threshold slope (SS), on-off current ratio (Ion/off) and parasitic capacitance, are extremely degraded due to several process and technological issues[7]-[9]....

    [...]

  • ...In order to reduce the above constraints and for simpler fabrication process, junction-less double gate field effect transistor (JL­ DGFET) is a promising candidate for ZRAM application[7]....

    [...]

Proceedings ArticleDOI
01 Dec 2007
TL;DR: A new generation of the single transistor floating body DRAM is introduced for the first time, largely based on the bipolar transistor existing in the MOS structure, with high margin, low-power consumption, and scalability.
Abstract: A new generation of the single transistor floating body DRAM is introduced for the first time. The new memory is largely based on the bipolar transistor existing in the MOS structure. The memory's main features are high margin, low-power consumption, and scalability.

212 citations


"Design of band-gap engineered silic..." refers background or methods in this paper

  • ...With the scaling of silicon technology node in deep nanometer regime, the fabrication of these fast, cheap and small single transistor in series with one capacitor (l T 11 C) embedded DRAM cells have been major problem for the semiconductor manufacturing industry in recent times[ 1 ]-[4]....

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  • ...The hysteresis current-voltage characteristics has been displayed when floating body field effect transistor (FET) and gated thyristor have been demonstrated[3],[4]....

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Journal ArticleDOI
E. Yoshida1, Tetsu Tanaka1
TL;DR: In this article, a capacitorless one-transistor (1T)-dynamic random access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated.
Abstract: A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude and a write speed within several nanoseconds. The capacitorless 1T DRAM is the most promising technology for high-performance embedded-DRAM large-scale integration.

197 citations

Journal ArticleDOI
TL;DR: In this paper, a one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated and measured and analyzed using a 96 kb array diagnostic monitor (ADM).
Abstract: A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a large-scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation.

43 citations


"Design of band-gap engineered silic..." refers background or methods in this paper

  • ...The continuous downscaling trend for performance advancement of conventional metal oxide semiconductor field effect transistor (MOSFET) is limited by short channel effects (SCEs) such as: sub-threshold slope (SS), on-off current ratio (Ion/off) and parasitic capacitance, are extremely degraded due to several process and technological issues[7]-[9]....

    [...]

  • ...The value of � is calculated by method proposed by Armstrong et al.[9] with increased drain bias....

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