Design of band-gap engineered silicon-germanium Junctionless Double-gate FET for ZRAM application
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"Design of band-gap engineered silic..." refers background in this paper
...The continuous downscaling trend for performance advancement of conventional metal oxide semiconductor field effect transistor (MOSFET) is limited by short channel effects (SCEs) such as: sub-threshold slope (SS), on-off current ratio (Ion/off) and parasitic capacitance, are extremely degraded due to several process and technological issues[7]-[9]....
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...In order to reduce the above constraints and for simpler fabrication process, junction-less double gate field effect transistor (JL DGFET) is a promising candidate for ZRAM application[7]....
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212 citations
"Design of band-gap engineered silic..." refers background or methods in this paper
...With the scaling of silicon technology node in deep nanometer regime, the fabrication of these fast, cheap and small single transistor in series with one capacitor (l T 11 C) embedded DRAM cells have been major problem for the semiconductor manufacturing industry in recent times[ 1 ]-[4]....
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...The hysteresis current-voltage characteristics has been displayed when floating body field effect transistor (FET) and gated thyristor have been demonstrated[3],[4]....
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197 citations
43 citations
"Design of band-gap engineered silic..." refers background or methods in this paper
...The continuous downscaling trend for performance advancement of conventional metal oxide semiconductor field effect transistor (MOSFET) is limited by short channel effects (SCEs) such as: sub-threshold slope (SS), on-off current ratio (Ion/off) and parasitic capacitance, are extremely degraded due to several process and technological issues[7]-[9]....
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...The value of � is calculated by method proposed by Armstrong et al.[9] with increased drain bias....
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