Design of Basic Building Blocks of ALU
01 Jan 2016-pp 315-327
TL;DR: The carry-select adder with K–S algorithm is found to be one of the fastest algorithms for addition and Urdhva-Tiryagbhyam Karastuba algorithm for multiplication, which are the most important operations in any central processing unit.
Abstract: There were no limits for speed of operation of arithmetic/logical circuits. One can always try to increase their speed. There were many proposed algorithms, which would work fast to specified arithmetic operations. So, there is the need for the implementation of a faster design by putting these fastest algorithms in a single ALU. The carry-select adder with K–S algorithm is found to be one of the fastest algorithms for addition and Urdhva-Tiryagbhyam Karastuba algorithm for multiplication, which are the most important operations in any central processing unit. We have used QUARTUS-II software. This design can be used where high speed computation is needed. This design would work for unsigned, fixed point, 8-bit operations. We have taken the different adder circuits and compared their performance. These circuits are the basic elements or building blocks of an ALU. The circuits have been simulated using 90 nm technology of Cadence and Quartus II EP2C20F484C7. Adders can be implemented using EX-OR/EX-XNOR gates, transmission gates, HSD (High Speed Domino) technique, domino logic. Parallel feedback carry adder, ripple carry adder, carry look ahead adder, carry-select adder are some of the adders that been implemented using Cadence and Quartus-II. We found that 10T PFCA is efficient compared to 11 T PFCA to some extent. Adders based on XOR and XNOR gates have the least delay compared to the other adders that we have used.
References
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TL;DR: This paper uses a technique called recursive doubling in an algorithm for solving a large class of recurrence problems on parallel computers such as the Iliac IV.
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1,264 citations
TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.
Abstract: Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
377 citations
29 Feb 2012
TL;DR: The pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area is presented and ripple carry adder is presented.
Abstract: Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12 µm 6metal layer CMOS technology using microwind tool.
128 citations
11 Aug 2005
TL;DR: In this paper, different possibilities of implementing the Karatsuba multiplier for polynomials over FPGAs are investigated. But the authors focus on the problem of implementing finite fields of characteristic 2.
Abstract: We study different possibilities of implementing the Karatsuba multiplier for polynomials over ${\mathbb F}_{2}$ on FPGAs.
This is a core task for implementing finite fields of characteristic 2. Algorithmic and platform dependent optimizations yield efficient hardware designs. The resulting structure is hybrid in two different aspects. On the one hand, a combination of the classical and the Karatsuba methods decreases the number of bit operations. On the other hand, a mixture of sequential and combinational circuit design techniques includes pipelining and can be adapted flexibly to time-area constraints. The approach—both theory and implementation—can be viewed as a further step towards taming the machinery of fast algorithmics for hardware applications.
55 citations
26 Mar 2017
TL;DR: In this article, a vedic multiplier using Urdhva Tiryagbhyam sutra in Xilinx ISE is proposed and the design takes lesser time for operation than currently available multipliers.
Abstract: Today's technology has raised demand for Fast and real time signal processing operation. Multiplication is one of the most important arithmetic operations. In this paper, we have proposed design of vedic multiplier using Urdhva Tiryagbhyam sutra in Xilinx ISE. This design takes lesser time for operation than currently available multipliers .It encompasses wide era of image processing and digital signal processing in much efficient way with increase in speed and thus leading to higher performance rating
24 citations