Book ChapterDOI
Design of Efficient Approximate Multiplier for Image Processing Applications
C. Sai Revanth Reddy,U. Anil Kumar,Syed Ershad Ahmed +2 more
- pp 511-518
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TLDR
A new truncation scheme and an error correction term which are applied to recursive multiplier architecture and prove that the proposed multiplier performs better compared to the existing multipliers.Abstract:
Approximate computing is an emerging paradigm to create energy-efficient computing systems. Most of the image processing applications are inherently error-resilient and can tolerate the error up to a certain limit. In such applications, energy can be saved by pruning the data path modules such as a multiplier. In this paper, we propose a new truncation scheme and an error correction term which are applied to recursive multiplier architecture. Further, truncation method and correction term that compensates the error in the proposed approximate multiplier significantly reduce the area, delay and power. Finally, the proposed multiplier is validated on an image sharpening algorithm. Simulations carried out clearly prove that the proposed multiplier performs better compared to the existing multipliers.read more
References
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Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Journal Article
Multiplication of Multidigit Numbers on Automata
Anatoly A. Karatsuba,Yu. Ofman +1 more
Journal ArticleDOI
Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications
TL;DR: It is shown that these proposed Bio-inspired Imprecise Computational blocks (BICs) can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.
Proceedings ArticleDOI
Trading Accuracy for Power with an Underdesigned Multiplier Architecture
TL;DR: A novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block, that can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods is proposed.
Journal ArticleDOI
Multipliers With Approximate 4–2 Compressors and Error Recovery Modules
Minho Ha,Sunggu Lee +1 more
TL;DR: The proposed design, even with the additional error recovery module, is more accurate, requires less hardware, and consumes less power than previously proposed 4–2 compressor-based approximate multiplier designs.