Design of Efficient Reversible Multiplier
01 Jan 2013-pp 571-579
TL;DR: The 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM, which is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost.
Abstract: Reversible logic is emerging computing paradigm with applications in Ultra-low power Nano computing, quantum computing, Low power CMOS design, Optical Information Processing, Bioinformatics etc. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct NxN reversible multiplier circuit.
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TL;DR: In this paper, the authors proposed a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier, which utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm.
Abstract: A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60 to 90 % in ancilla qubits count over the existing work on reversible quantum integer multipliers.
44 citations
TL;DR: A binary tree-based design methodology for an $$N \times N$$N×N reversible multiplier performs the addition of partial products in parallel using the reversible ripple adders with zero ancilla bit and zero garbage bit, thereby, minimizing the number of anCilla and garbage bits used in the design.
Abstract: Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipationless computing and low-power computing, etc. In reversible logic there exists a one-to-one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Reversible circuits of many qubits are extremely difficult to realize; thus, reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature, researchers have proposed several designs of reversible multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and half adders for the addition of partial products increases the overhead in terms of the number of ancilla inputs and garbage outputs. This paper presents a binary tree-based design methodology for an $$N \times N$$N×N reversible multiplier. The proposed binary tree-based design methodology for $$N \times N$$N×N reversible multiplier performs the addition of partial products in parallel using the reversible ripple adders with zero ancilla bit and zero garbage bit; thereby, minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows a 17.86---60.34 % improvement in terms of ancilla inputs; and 21.43---52.17 % in terms of garbage outputs compared to all the existing reversible multiplier designs. The methodology is also extended to the design of $$N \times N$$N×N reversible signed multiplier based on modified Baugh---Wooley multiplication methodology.
21 citations
01 Aug 2015
TL;DR: This paper presents a novel method to reduce garbage outputs and ancilla inputs of reversible quantum multipliers by converts some garbage outputs of the previous calculation to zeros, which are then served as ancillas inputs of the later calculation.
Abstract: Reversible logic is widely used in optical information processing, bioinformatics and quantum computing etc. Reversible logic requires ancilla inputs and garbage outputs to keep reversibility. However, it needs to reduce the number of these logic bits in complex designs, such as reversible quantum multipliers. In the existing literatures, researchers have optimized the multi-operand addition part and the partial product generation part of reversible quantum multipliers separately, which produce considerable overhead in terms of garbage outputs and ancilla inputs. This paper presents a novel method to reduce garbage outputs and ancilla inputs of reversible quantum multipliers. The proposed methodology converts some garbage outputs of the previous calculation to zeros, which are then served as ancilla inputs of the later calculation. In order to verify the proposed method, we apply it to two typical reversible quantum multiplier designs. Results show that the proposed method can greatly reduce the number of garbage outputs and ancilla inputs compared to the existing designs.
5 citations
Cites background or methods from "Design of Efficient Reversible Mult..."
...Some garbage outputs of the reversible half adders and the reversible full adders in the existing designs [1], [4], [8], [9], [10], [11], [12], [13] are equal to some partial products, so they can be converted to zeros with Toffoli gates and then be used in the later calculation....
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...The method can greatly reduce the number of garbage outputs and ancilla inputs compared to the designs in [1], [4], [8], [9], [10], [11], [12], [13]....
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...The reversible half adder is realized by the Peres gate and the reversible full adder is realized by the MKG gate [13], the HNG gate [4], [12], the PFAG gate [1], [9], [11], or the DPG gate [8], [10], which is shown in Fig....
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...The methods in [1], [4], [8], [9], [10], [11], [12], [13] can reduce the use of the reversible quantum gate and the depth of the reversible quantum multiplier, but need more ancilla inputs and produce more garbage outputs....
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...For [8], it only needs to duplicate each bit of X, so the number of garbage outputs and the number of ancilla inputs in [8] are both 12 fewer than that of [4]....
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TL;DR: This work is the first in the literature to use Baugh-Wooley algorithm using reversible logic, and a new 5 × 5 reversible multiplier cell is proposed which will be useful in designing Baugh and Wooley multiplier.
Abstract: In today’s digital era, developing digital circuits is bounded by the research towards investigating various nano devices. This paper provides the design of compact Baugh-Wooley multiplier using reversible logic. Even though various researches have been done for designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. In this work, a new 5 × 5 reversible multiplier cell is proposed which will be useful in designing Baugh-Wooley multiplier. The proposed single multiplier cell is able to perform addition of a 1 × 1 product with the sum and carry from the previous cell. This reversible multiplier cell is useful in building up regularity in the array multipliers. The Toffoli gate synthesis of the proposed reversible multiplier cell is also given.
5 citations
Cites background from "Design of Efficient Reversible Mult..."
...In [8], the authors have proposed a new reversible gate called as RAM gate....
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...In [5], the design requires a total of 40 reversible gates, [9] requires 42, total number of gates required is 44 in [7] and in [8] the number of gates required is 32 gates....
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07 Mar 2019
TL;DR: A system which employs Vedic multipliers and reversible gates to perform multiplications with increased throughput and using very little power is proposed.
Abstract: There is an ever increasing demand for low-power and high-speed designs due to the emergence of portable, handheld gadgets which run on batteries. More and more research works in VLSI are concentrated on different methodologies to reduce the power consumption of a system and also increase its throughput. Multiplication is an important operation in almost all computations. Design of multipliers with low power utilization and increased throughput will lead to systems with reduced power usage and high speed. Vedic Multipliers based on the Urdhava Tiryakbhyam sutra delivers results faster than the customary methods. Reversible logic gates when used in a circuit lead to little or no power dissipation. The paper proposes a system which employs Vedic multipliers and reversible gates to perform multiplications with increased throughput and using very little power. The designed system is optimized by combining the low power strategy of reversible logic and the high speed calculation of Urdhava Tiryakbhyam Vedic multiplier.
3 citations
Cites background from "Design of Efficient Reversible Mult..."
...These circuits consume very little power during computations [12]....
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References
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TL;DR: Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
Abstract: It is argued that computing machines inevitably involve devices which perform logical functions that do not have a single-valued inverse. This logical irreversibility is associated with physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function. This dissipation serves the purpose of standardizing signals and making them independent of their exact logical history. Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
3,629 citations
IBM1
TL;DR: This result makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step.
Abstract: The usual general-purpose computing automaton (e.g.. a Turing machine) is logically irreversible- its transition function lacks a single-valued inverse. Here it is shown that such machines may he made logically reversible at every step, while retainillg their simplicity and their ability to do general computations. This result is of great physical interest because it makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step. In the first stage of its computation the logically reversible automaton parallels the corresponding irreversible automaton, except that it saves all intermediate results, there by avoiding the irreversible operation of erasure. The second stage consists of printing out the desired output. The third stage then reversibly disposes of all the undesired intermediate results by retracing the steps of the first stage in backward order (a process which is only possible because the first stage has been carried out reversibly), there by restoring the machine (except for the now-written output tape) to its original condition. The final machine configuration thus contains the desired output and a reconstructed copy of the input, but no other undesired data. The foregoing results are demonstrated explicitly using a type of three-tape Turing machine. The biosynthesis of messenger RNA is discussed as a physical example of reversible computation.
3,497 citations
"Design of Efficient Reversible Mult..." refers background in this paper
...Charles Bennett [2] showed that energy loss could be avoided or even eliminated if the computations are carried out in reversible logic and also proved that circuit built from reversible gates have zero power dissipation....
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Book•
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01 Jan 2001
TL;DR: Conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation and proves that universal computing capabilities are compatible with the reversibility and conservation constraints.
Abstract: Conservative logic is a comprehensive model of computation which explicitly reflects a number of fundamental principles of physics, such as the reversibility of the dynamical laws and the conservation of certain additive quantities (among which energy plays a distinguished role). Because it more closely mirrors physics than traditional models of computation, conservative logic is in a better position to provide indications concerning the realization of high-performance computing systems, i.e., of systems that make very efficient use of the "computing resources" actually offered by nature. In particular, conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation. After establishing a general framework, we discuss two specific models of computation. The first uses binary variables and is the conservative-logic counterpart of switching theory; this model proves that universal computing capabilities are compatible with the reversibility and conservation constraints. The second model, which is a refinement of the first, constitutes a substantial breakthrough in establishing a correspondence between computation and physics. In fact, this model is based on elastic collisions of identical "balls" and thus is formally identical with the atomic model that underlies the (classical) kinetic theory of perfect gases. Quite literally, the functional behavior of a general-purpose digital computer can be reproduced by a perfect gas placed in a suitably shaped container and given appropriate initial conditions.
1,888 citations
TL;DR: The physical limitations due to quantum mechanics on the functioning of computers are analyzed in this paper, where the physical limitations of quantum mechanics are discussed and the physical limits of quantum computing are analyzed.
Abstract: The physical limitations, due to quantum mechanics, on the functioning of computers are analyzed.
1,717 citations
Proceedings Article•
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14 Jul 1980
TL;DR: According to a physical interpretation, the central result of this paper is that i¢ is ideally possible to build sequential c/rcuits with zero internal power dissipation.
Abstract: The theory of reversible computing is based on invertib|e primitives and composition rules that preserve invertibility. With these constraints, one can still satisfactorily deal with both functional and structural aspects of computing processes; at the same time, one attains a closer correspondence between the behavior of abstract computing systems and the microscopic physical laws (which are presumed to be strictly reversible) that underly any concrete implementation of such systems. According to a physical interpretation, the central result of this paper is that i¢ is ideally possible to build sequential c/rcuits with zero internal power dissipation.
1,357 citations
"Design of Efficient Reversible Mult..." refers background in this paper
...Toffoli gate [5] is one of the most popular reversible gates and has quantum cost of five....
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