# Design of exclusive or sum-of-products (ESP) logic arrays with universal tests for detecting stuck-at and bridging faults

TL;DR: In this article, the authors proposed a technique of augmenting the network with some additional observation points which take care of otherwise undetectable bridging faults in AND-EXOR arrays, which are different from the arrays based on the Reed-Muller canonic (RMC) expansion of functions.

Abstract: The detection problem of bridging faults in AND-EXOR arrays is considered in this paper in a new framework. These AND-EXOR arrays are different from the arrays based on the so-called Reed-Muller canonic (RMC) expansion of functions. The multiple stuck-at fault detection test set in such arrays as already derived by Pradhan[1] has been utilized to detect bridging faults. One most important advantage of this test set is that it is independent of the function realized and it has a simple algebraic structure and hence can be generated easily. As this conventional test set is insufficient to detect all bridging faults, we propose a technique of augmenting the network with some additional observation points which take care of otherwise undetectable bridging faults.

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TL;DR: This paper presents a testability enhancement technique suited for AND-EXOR based logic networks that facilitates easy detection of stuck-at and bridging faults by a universal test set and solves an open problem of designing auniversal test for a tree-based AND- EXOR circuit.

Abstract: This paper presents a testability enhancement technique suited for AND-EXOR based logic networks that facilitates easy detection of stuck-at and bridging faults by a universal test set. Both cascaded and tree implementations of the EXOR-part are considered. The AND-EXOR based circuit implemented with a cascaded EXOR-part requires a universal test set of size (2n+6) for an n-variable function implementation. For Generalized Reed-Muller (GRM) implementation, this test set detects all single stuck-at and bridging faults (both OR-type and AND-type) and also large number of multiple bridging faults. For an Exclusive-OR Sum-of-Products (ESOP) implementation, a few single bridging faults may remain untested under this test set, occurrence of which can be minimized by employing an appropriate design and layout technique. Next, it is shown that an AND-EXOR network with a tree-based EXOR-part can be tested for similar faults by a universal test set of size (2n+8). This paper also solves an open problem of designing a universal test for a tree-based AND-EXOR circuit. Since the EXOR-tree has depth of (@?log"2s@?+1), where s is the number of product terms in the given AND-EXOR expression, this tree-based design reduces the circuit delay significantly compared to cascaded EXOR implementation. In both the cases, the test set can be stored in a ROM on-chip for built-in self-test (BIST) purposes. For several benchmark circuits, the universal test set is found to be much smaller in size than the ATPG-generated test sets.

13 citations

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05 Jan 2004

TL;DR: A testable realization of Generalized Reed-Muller (GRM) or EXOR Sum-of-Products (ESOP) expression has been proposed that admits a combined universal test set of size (2n+6) for detection of stuck-at and bridging faults.

Abstract: A testable realization of Generalized Reed-Muller (GRM) or EXOR Sum-of-Products (ESOP) expression has been proposed that admits a combined universal test set of size (2n+6) for detection of stuck-at and bridging faults. For GRM implementation, the test set detects all single stuck-at and bridging faults (both OR and AND type) and a large number of multiple bridging faults. For ESOP, a few single bridging faults may remain untested, occurrence of which can be avoided by employing a design and layout technique. The test set is independent of the function and the circuit-under-test and can be stored in a ROM on chip for built-in self-test. For several benchmark circuits, the size of the test set is found to be much smaller than an ATPG-generated test set or those of the previous methods.

12 citations

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TL;DR: A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties of "easily testable networks".

Abstract: Desirable properties of "easily testable networks" are given. A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties. If only permanent stuck-at-0 (s-a-0) or stuck-at-1 (s-a-1) faults occur in a single AND gate or only a single EXCLUSIVE-OR gate is faulty, the following results are derived on fault detecting test sets for the proposed networks: 1) only (n/4) tests, independent of the function being realized, are required if the primary inputs are fault-free; 2) only 2n, additional inputs (which depend on the function realized) are required if the primary inputs can be faulty, where n, is the number of variables appearing in even number of product terms in the Reed-Muller canonical expansion of the function; and 3) the additional 2ne inputs are not required if the network is provided with an observable point at the output of an extra AND gate.

278 citations

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Hewlett-Packard

^{1}TL;DR: The commonly used stuck-at fault fails to model logic circuit shorts, so Bridging faults are defined to model these circuit mal-functions.

Abstract: The commonly used stuck-at fault fails to model logic circuit shorts. Bridging faults are defined to model these circuit mal-functions. This model is based on wired logic which is a characteristic of many logic families such as resistor-transistor logic (RTL), diode transistor logic (DTL), emitter-coupled logic (ECL), etc. It does not apply to TTL circuits. The model also limits to fan-out-free leads.

248 citations

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TL;DR: In this article, a branch-and-bound algorithm is developed for selecting an optimal (or near-optimal) set of q test points in fanout-free networks, and some difficulties associated with test point placement in general networks are pointed out.

Abstract: The problem of selecting test points to reduce the number of tests for fault detection in combinational logic networks is examined. A method is presented for labeling the lines of a network. Procedures are described for obtaining a minimal labeling, i.e., one corresponding to a minimal set of tests, for fanout-free circuits and for a restricted class of circuits with fanout. Using these procedures, a branch-and-bound algorithm is developed for selecting an optimal (or near-optimal) set of q test points in fanout-free networks. Some difficulties associated with test point placement in general networks are pointed out. It is shown that the labeling approach is also applicable to the problem of selecting and placing control logic.

114 citations

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TL;DR: This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms for obtaining minimal modulo 2 or complement modulo2 sum-of- products expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.

Abstract: This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms. In particular, algorithms are presented for obtaining minimal modulo 2 or complement modulo 2 sum-of- products (or sums) expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.

82 citations

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01 Jan 1982

TL;DR: The bj coefficient map is introduced, the entries in which are the {0, l} coefficient values of the Reed-Muller Exclusive-OR expansions by which any given combinatorial function may be expressed, and provides a deeper insight into the coefficient relationships which arise when input variables are complemented in any Exclusive- OR expansion.

Abstract: A new geometric format, the bj coefficient map, is here introduced, the entries in which are the {0, l} coefficient values of the Reed-Muller Exclusive-OR expansions by which any given combinatorial function may be expressed. Although similar in format to the classic Karnaugh map, the bj map entries do not represent the function output in the same manner as do the minterm entries plotted on a Karnaugh map. It is shown that this coefficient map structure may readily be used to generate any required Exclusive-OR realisation of a given function, and provides a deeper insight into the coefficient relationships which arise when input variables are complemented in any Exclusive-OR expansion.

67 citations