Design of FinFET based frequency synthesizer
01 Dec 2015-pp 1-5
TL;DR: A frequency synthesizer capable of synthesizing an input clock frequency of 500 MHz to an output frequency of 1 GHz is implemented using FinFET with a lock in time of 254 ns.
Abstract: Miniaturization in the geometry of CMOS technology improves IC performance but beyond certain limit, scaling of CMOS may be quite challenging due to various short channel effects. To overcome such issues double gate (DG) CMOS or FinFET are used because of its ability to minimize short channel effects. This paper presents the designing of frequency synthesizer using phase locked loop (PLL) based on FinFET technology. Here we have used shorted gate FinFET for designing the circuits. A frequency synthesizer capable of synthesizing an input clock frequency of 500 MHz to an output frequency of 1 GHz is implemented using FinFET with a lock in time of 254 ns. The circuits are implemented on Cadence ®Virtuoso using 32nm FinFET technology and 1V power supply.
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22 Aug 1997
TL;DR: Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.
Abstract: The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.
2,724 citations
"Design of FinFET based frequency sy..." refers background or methods in this paper
...Here, PFD [4] is used to detect the phase error between the input reference clock and output clock from the frequency divider circuit....
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...UP and DOWN into a single current signal to drive the loop filter [4]....
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...The basic purpose of a PLL is to generate a clock signal which is in phase with respect to the reference clock signal [4]....
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...The second order loop filter is employed mostly because of its efficiency compared to a first order system in terms of noise suppression [4]....
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...Some of these applications includes radios, mobile phones other wireless devices [4]....
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TL;DR: This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology.
Abstract: Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of /spl plusmn/320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW. >
199 citations
"Design of FinFET based frequency sy..." refers background in this paper
...However, the scaling of CMOS technology reaches its limit due to the short channel effects [1]....
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24 Jul 2006
TL;DR: The gate sizing of finFET devices is investigated, and a comparison with 32nm bulk CMOS is provided, showing thatfinFET circuits are superior in performance and produce less static power when compared to 32nm circuits.
Abstract: FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. We investigate in this paper the gate sizing of finFET devices, and we provide a comparison with 32nm bulk CMOS. Wider finFET devices are built utilizing multiple parallel fins between the source and drain. Independent gating of the finFET's double gates allows significant reduction in leakage current. We perform temperature-aware circuit optimization by modeling delay using temperature-dependent parameters, and by imposing constraints that limit the maximum allowable number of parallel fins. We show that finFET circuits are superior in performance and produce less static power when compared to 32nm circuits.
91 citations
"Design of FinFET based frequency sy..." refers background in this paper
...Some of the main advantages of FinFET include higher Ion/Ioff ratio and low value of intrinsic gate capacitances [2]....
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29 Aug 2005
TL;DR: A 1 V wireless SoC embedding an RF transceiver, a sensor interface, a 6.4 MHz RISC micro-controller with an 8k instruction SRAM and a power management unit is reported.
Abstract: A 1 V wireless SoC embedding an RF transceiver, a sensor interface, a 6.4 MHz RISC micro-controller with an 8k instruction SRAM and a power management unit is reported. The radio supports 25 kb/s FSK and 2 kb/s OOK modulations in the 433/868 MHz bands. In the 433 MHz band, the receiver draws 2.1 mA while providing a sensitivity of -108 dBm and the transmitter draws 27.6 mA for an output power of 10.5 dBm.
72 citations
TL;DR: A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs and alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression.
Abstract: A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and $\Delta \Sigma $ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of $-$ 104 dBc/Hz and 1.5 ps $_{\rm rms}$ integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of $-$ 225.8 dB.
47 citations
"Design of FinFET based frequency sy..." refers background or methods in this paper
...The variety of low power PLL based frequency synthesizer using CMOS has been developed for the low power consumption and low phase noise [5-10]....
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...To improve the phase noise performance of the PLL, a hybrid phase/current-mode phase interpolator using 65 nm CMOS technology is presented in [9]....
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...(Output clock is shown as a line with the symbol and the reference clock is the line without symbol) Ref [16] Ref [9] Ref [17] This Work...
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