Design of FPGA-Based QPP Interleaver for LTE/LTE-Advanced Application

Abstract: The Definitive Guide to LTE Technology Long-Term Evolution (LTE) is the next step in the GSM evolutionary path beyond 3G technology, and it is strongly positioned to be the dominant global standard for 4G cellular networks. LTE also represents the first generation of cellular networks to be based on a flat IP architecture and is designed to seamlessly support a variety of different services, such as broadband data, voice, and multicast video. Its design incorporates many of the key innovations of digital communication, such as MIMO (multiple input multiple output) and OFDMA (orthogonal frequency division multiple access), that mandate new skills to plan, build, and deploy an LTE network. In Fundamentals of LTE, four leading experts from academia and industry explain the technical foundations of LTE in a tutorial style providing a comprehensive overview of the standards. Following the same approach that made their recent Fundamentals of WiMAX successful, the authors offer a complete framework for understanding and evaluating LTE. Topics includeCellular wireless history and evolution: Technical advances, market drivers, and foundational networking and communications technologiesMulticarrier modulation theory and practice: OFDM system design, peak-to-average power ratios, and SC-FDE solutionsFrequency Domain Multiple Access: OFDMA downlinks, SC-FDMA uplinks, resource allocation, and LTE-specific implementationMultiple antenna techniques and tradeoffs: spatial diversity, interference cancellation, spatial multiplexing, and multiuser/networked MIMOLTE standard overview: air interface protocol, channel structure, and physical layersDownlink and uplink transport channel processing: channel encoding, modulation mapping, Hybrid ARQ, multi-antenna processing, and morePhysical/MAC layer procedures and scheduling: channel-aware scheduling, closed/open-loop multi-antenna processing, and morePacket flow, radio resource, and mobility management: RLC, PDCP, RRM, and LTE radio access network mobility/handoff procedures

Abstract: An interleaver is a critical component for the channel coding performance of turbo codes. Algebraic constructions are of particular interest because they admit analytical designs and simple, practical hardware implementation. Contention-free interleavers have been recently shown to be suitable for parallel decoding of turbo codes. In this correspondence, it is shown that permutation polynomials generate maximum contention-free interleavers, i.e., every factor of the interleaver length becomes a possible degree of parallel processing of the decoder. Further, it is shown by computer simulations that turbo codes using these interleavers perform very well for the Third Generation Partnership Project (3GPP) standard

Abstract: We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations

Abstract: This paper describes the energy-efficient implementation of a high performance parallel radix-4 turbo decoder, which is designed to support multiple fourth-generation (4G) wireless communication standards such as Mobile WiMAX and 3GPP-LTE We propose a new hardware architecture that can share hardware resources for the two standards It mainly consists of eight retimed radix-4 soft-input soft-output (SISO) decoders to achieve high throughput and a dual-mode parallel hardware interleaver to support both almost regular permutation (ARP) and quadratic polynomial permutation (QPP) interleavers defined in the two standards A prototype chip supporting both Mobile WiMAX and 3GPP-LTE standards is fabricated in a 013µm CMOS technology with eight metal layers The decoder core occupies 107mm2 and can exhibit a decoding rate of more than 100Mb/s with eight iterations while achieving an energy efficiency of 031nJ/bit/iter