Design of FPGA-Based QPP Interleaver for LTE/LTE-Advanced Application
01 Jan 2022-pp 139-153
TL;DR: In this article, a low-complexity hardware solution to implement the interleaver address generator is proposed, which can provide low complexity hardware solution for implementing the address generator using ModelSim XE-III software.
Abstract: Modern wireless communication systems have witnessed increasing use of channel coding techniques to enhance the throughput and to reduce latency. Interleavers are playing an important role to make the communication systems more robust and resilient in such channel coding approaches. The Long-Term Evolution (LTE)/LTE-Advanced of the 3rd Generation Partnership Project (3GPP) uses Quadrature Permutation Polynomial (QPP) interleaver in its Turbo coding scheme. The address generator of the interleaver contains a quadratic expression having square and modulus function whose direct digital hardware is not yet available in the literature. A novel algorithm has now been proposed which can provide low complexity hardware solution to implement the interleaver address generator. This paper describes VHDL model and timing simulation of the proposed address generator using ModelSim XE-III software. Due to absence of implementation results in the literature, comparison of this work is made by implementing conventional LUT-based technique on the same FPGA. Such comparison shows better FPGA resource utilization by 71.16% and improved operating speed by 82.26% in favour of the novel proposed technique.
References
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TL;DR: A robust path metric initialization is given to improve the performance loss in small blocks and high parallelism in the parallel architecture for the turbo decoder using the quadratic permutation polynomial interleaver.
Abstract: This brief presents a parallel architecture for the turbo decoder using the quadratic permutation polynomial interleaver. The supported block size ranges from 40 to 6144 with an increment of 8, and thus, it includes 188 sizes in the 3rd Generation Partnership Project Long Term Evolution standard. The proposed design can allow one, two, four, or eight soft-in/soft-out decoders to process each block with configurable iterations. To support all data transmissions in the parallel design, a multistage network with low complexity is also utilized. Moreover, a robust path metric initialization is given to improve the performance loss in small blocks and high parallelism. After fabrication in the 90-nm process, the 2.1-mm2 chip can achieve 130 Mb/s with 219 mW for the size-6144 block and eight iterations.
56 citations
TL;DR: A flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems.
Abstract: To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA +/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.
41 citations
16 May 2011
TL;DR: A high-speed hardware implementation of a random number generator that produces more than 11 million random numbers per second on the SRC-6 reconfigurable computer and is suitable for RNS number system applications.
Abstract: We show a high-speed hardware implementation of $x$ mod $z$ that can be pipelined in $O(n-m)$ stages, where $x$ is represented in $n$ bits and $z$ is represented in $m$ bits. It is suitable for large $x$. We offer two versions. In the first, the value of $z$ is fixed by the hardware. For example, using this circuit, we show a random number generator that produces more than 11 million random numbers per second on the SRC-6 reconfigurable computer. In the second, $z$ is an independent input. This is suitable for RNS number system applications, for example. The second version can be pipelined in $O(n)$ stages.
28 citations
23 Nov 2015
TL;DR: A novel algorithm is introduced to combine three of these CRC circuits into one in order to minimize the total area of the transceiver, guaranteeing a considerable reduction in the dynamic power of the system.
Abstract: Long Term Evolution Advanced (LTE-A) uses four different kinds of Cyclic Redundancy Check (CRC) to verify the integrity of the transmitted data, which implies using four circuits for each CRC in the transceiver system. In this paper, a novel algorithm is introduced to combine three of these CRC circuits into one in order to minimize the total area of the transceiver. This method will insure a considerable reduction in the dynamic power of the system. The new circuit is designed in a parallel fashion and is tested on an Altera FPGA platform to verify its power consumption and number of used gates hence, the total reduction in size. The result shows a good reduction in the number of used logic gates.
7 citations