Design of High-Speed Turbo Product Code Decoder
01 Jan 2021-pp 175-186
TL;DR: In this paper, a fast Chase decoder has been proposed to improve the speed by replacing the ripple carry adder in the design with a fast adder, and an increase in computation speed of 5% has been achieved.
Abstract: In the field of digital communication, there has always been a requirement for an efficient, low complex, and high-speed error control encoder and decoder. Many such encoders and decoders for different error control codes have been proposed in the literature by researchers. However, developing such CODECs whose performance can be suitable for the requirements of modern communication systems is still an open research problem. In this paper, one such decoder, namely fast Chase decoder proposed in the literature, has been studied. The hardware design of the decoder has been done and verified with results from MATLAB simulations. An attempt has been made to improve the speed by replacing the ripple carry adder in the design with a fast adder. The hardware architecture is implemented in Xilinx XC7A35T platform, and an increase in computation speed of 5% has been achieved.
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01 Jan 2022
TL;DR: In this paper , the authors demonstrate the VERILOG implementation targeted for Artix-7 board, various error coding, and correction methodologies in the view of hardware storage using field programmable gate array (FPGA), thereby providing the readers an insight into the performance and advantages offered by these techniques.
Abstract: Error coding is a method of detecting and correcting errors that ensures the detection of information bits and error recovery in case of damage. Encoding is done using mathematical techniques that pad extra bits to data which aid the recovery of the original message. Several error coding techniques offering different error rates and recovery capabilities are employed in modern-day communication systems facilitating error-free transmission of information bits. Hardware-based implementations of these error coding techniques for robust memory systems and processors has become imperative due to error resistance compared to their software counterparts. In this work, the authors demonstrate the VERILOG implementation targeted for Artix-7 board, various error coding, and correction methodologies in the view of hardware storage using field programmable gate array (FPGA), thereby providing the readers an insight into the performance and advantages offered by these techniques. Their performance in terms of power consumption and utilization is evaluated and analyzed.
01 Dec 2022
TL;DR: In this article , a modified partially parallel polar encoder architecture is proposed, where the registers that are used for inducing the parallelism in the architecture are replaced with pulsed latches, making the whole architecture low power and area efficient.
Abstract: Polar codes are highly channel efficient with minimum hardware complexity with increasing code length, making them one of the most favorable error-correcting codes. There exist many architectures for both encoding and decoding of polar codes. In this paper a modified partially parallel polar encoder architecture is proposed. The registers that are used for inducing the parallelism in the architecture are replaced with pulsed latches, making the whole architecture low power and area efficient. The synthesis and simulation of the proposed architecture is carried out in Xilinx ISE for (16,k), (32,k) and (64,k) polar codes. Results show that the proposed architecture leads to an average reduction of 50% and 45% in power and gate count respectively.
01 Dec 2022
TL;DR: In this paper , a modified partially parallel polar encoder architecture is proposed, where the registers that are used for inducing the parallelism in the architecture are replaced with pulsed latches, making the whole architecture low power and area efficient.
Abstract: Polar codes are highly channel efficient with minimum hardware complexity with increasing code length, making them one of the most favorable error-correcting codes. There exist many architectures for both encoding and decoding of polar codes. In this paper a modified partially parallel polar encoder architecture is proposed. The registers that are used for inducing the parallelism in the architecture are replaced with pulsed latches, making the whole architecture low power and area efficient. The synthesis and simulation of the proposed architecture is carried out in Xilinx ISE for (16,k), (32,k) and (64,k) polar codes. Results show that the proposed architecture leads to an average reduction of 50% and 45% in power and gate count respectively.
References
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Proceedings Article•
01 Jan 1993
7,742 citations
01 Jan 1993
TL;DR: A new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
Abstract: A new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed. The turbo-code encoder is built using a parallel concatenation of two recursive systematic convolutional codes, and the associated decoder, using a feedback decoding rule, is implemented as P pipelined identical elementary decoders.<>
1,286 citations
TL;DR: An iterative decoding algorithm for any product code built using linear block codes based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration.
Abstract: This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information.
970 citations
TL;DR: An analysis of the weight distribution is used to explain the good performance results for these randomly interleaved SPC product codes in an additive white Gaussian noise channel.
Abstract: This paper considers the performance of iteratively decoded single parity check (SPC) multidimensional product codes in an additive white Gaussian noise channel. Asymptotic performance bounds are compared to simulation results. A new code structure based on SPC product codes is introduced. This structure involves interleaving between the encoding of each dimension in the product code. An analysis of the weight distribution is used to explain the good performance results for these randomly interleaved SPC product codes.
123 citations
TL;DR: This implementation re-orders the Chase algorithm's repeated decodings such that the inherent computational redundancy is greatly reduced without degrading performance.
Abstract: Turbo product codes (TPCs) provide an attractive alternative to recursive systematic convolutional (RSC)-based turbo systems. Rather than employ trellis-based decoders, an algebraic decoder may be repeatedly employed in a low-complexity, soft-input/soft-output errors-and-erasures decoder such as the Chase algorithm. Taking motivation from efficient forced erasure decoders, this implementation re-orders the Chase algorithm's repeated decodings such that the inherent computational redundancy is greatly reduced without degrading performance. The result is a highly efficient fast Chase implementation. The algorithm presented here is principally applicable to single error-correcting codes although consideration is also given to the more general case. The new decoder's value in practical turbo schemes is demonstrated via application to decoding of the (64,57,4) extended Hamming TPC.
82 citations