Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions
01 Jan 1974-
About: The article was published on 1974-01-01 and is currently open access. It has received 856 citations till now.
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Book•
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents
1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging
4,826 citations
IBM1
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
1,417 citations
Cites background from "Design of Ion-Implanted MOSFET'S wi..."
...For many years now, the shrinking of MOSFETs has been governed by the ideas of scaling [14], [15]....
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06 Mar 2014
TL;DR: If the drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance, a new wave of innovative and efficient computing devices will be created.
Abstract: Our challenge is clear: The drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. Continuing to scale compute performance will require the creation and effective use of new specialized compute engines, and will require the participation of application experts to be successful. If we play our cards right, and develop the tools that allow our customers to become part of the design process, we will create a new wave of innovative and efficient computing devices.
1,254 citations
Cites background from "Design of Ion-Implanted MOSFET'S wi..."
...Section 2 quickly reviews how computing became power limited, even before Dennard constantfield scaling [3] broke down, and explains the difficulties of using a technology change to fix our problems....
[...]
TL;DR: In this article, a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FET in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene.
Abstract: In the quest for higher performance, the dimensions of field-effect transistors (FETs) continue to decrease. However, the reduction in size of FETs comprising 3D semiconductors is limited by the rate at which heat, generated from static power, is dissipated. The increase in static power and the leakage of current between the source and drain electrodes that causes this increase, are referred to as short-channel effects. In FETs with channels made from 2D semiconductors, leakage current is almost eliminated because all electrons are confined in atomically thin channels and, hence, are uniformly influenced by the gate voltage. In this Review, we provide a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FETs in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene. We also describe tunnelling FETs that possess extremely low-power switching behaviour and explain how they can be realized using heterostructures of 2D semiconductors. Field-effect transistors (FETs) with semiconducting channels made from 2D materials are known to have fewer problems with short-channel effects than devices comprising 3D semiconductors. In this Review, a mathematical framework to evaluate the performance of FETs is outlined with a focus on the properties of 2D materials, such as graphene, transition metal dichalcogenides, phosphorene and silicene.
983 citations
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >
921 citations
References
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01 Apr 1972
TL;DR: In this paper, simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on, and these equations are used to find the transfer characteristics of complementary MOS inverters.
Abstract: Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.
435 citations
IBM1
TL;DR: In this article, the authors derived a closed-form threshold voltage equation for short-channel insulated-gate field-effect transistors (IGFETs) operating with source-to-substrate reverse bias.
Abstract: For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length. The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.
126 citations
TL;DR: In this article, a finite-difference scheme is presented for obtaining an approximate solution of a system of nonlinear elliptic partial differential equations describing the carrier distribution in such a device model.
Abstract: This paper is concerned with the mathematical details of a numerical model of the insulated-gate field-effect transistor; a computer-aided analysis of the device, based on this model, appears separately A finite-difference scheme is presented for obtaining an approximate solution of a system of nonlinear elliptic partial differential equations describing the carrier distribution in such a device model In particular, our scheme allows the device current, as a function of the applied bias voltages, to be reliably calculated The results of numerical experiments appraising the accuracy of the method are also included
120 citations
IBM1
TL;DR: In this paper, the authors describe short-channel devices (L_{eff} \sim 1 µ) designed by scaling down larger devices with desirable electrical characteristics, such as Lateral and vertical dimensions, doping level, and operating voltages and currents.
Abstract: Modern photolithographic technology offers the capability of fabricating MOSFET devices of micron dimensions and less. It is by no means obvious that such small devices can be designed with suitable electrical characteristics for LSI switchivg applications. In this talk we will describe short-channel devices ( L_{eff} \sim 1 µ) designed by scaling down larger devices with desirable electrical characteristics. Lateral and vertical dimensions, doping level, and operating voltages and currents are scaled in a self-consistent fashion. In this way small devices have been fabricated without the usual deleterious effects associated with short channels. The measured characteristics of these short-channel devices and the larger devices from which they were scaled will be compared.
108 citations
IBM1
TL;DR: A modified one-dimensional mathematical theory is proposed, to account for mechanisms of operation for an insulated gate field effect transistor (IGFET), that is in adequate agreement with a rigorous two-dimensional computer solution for this semiconductor problem.
Abstract: A two-dimensional mathematical analysis is presented of the mechanisms of operation for an insulated gate field effect transistor (IGFET). Included in this analysis are qualitative and quantitative comparisons between conventional one-dimensional theory and a rigorous two-dimensional computer solution for the IGFET. It is shown that many characteristics of device operation deduced from conventional theory cannot be verified on a two-dimensional basis because of mechanisms not presently taken into consideration by the theory. A modified one-dimensional mathematical theory is therefore proposed, to account for these mechanisms, that is in adequate agreement with a rigorous two-dimensional computer solution for this semiconductor problem.
53 citations