Design of LDO Regulator in CMOS 45nm Technology

TLDR: It is demonstrated that in these LDOs the output voltage might be higher than the input reference voltage at minimum load current, and both the circuits begin "to follow" to achieve desired voltage with respect to load current depending on bias voltage.

Abstract: The transistor model is designed for outline of two different LDO Regulators having a differential stage stacked by current amplifier and the voltage feedback. The principal LDO has a consistent bias current. The LDOs were analysed to verify the transistors operations from weak inversion to strong inversion. It is demonstrated that in these LDOs the output voltage might be higher than the input reference voltage at minimum load current, and both the circuits begin "to follow" to achieve desired voltage with respect to load current depending on bias voltage. This paper additionally concentrates on outlining a particular LDO Regulator to fulfill the given requirements. The circuits were intended for 45 nm gpdk CMOS Technology and simulated in CADENCE Spectre tool.