Design of optimal final adder for parallel multiplier
21 Jul 2011-pp 436-441
TL;DR: To reduce the middle order partial product delay taking the optimal adder which is having high speed, on considering the BEC-1 adders, putting EBS adder in a unsigned multiplier using DADDA algorithm shows better result.
Abstract: The partial products in the normal multiplier is produced from the product of multiplier and the multiplicand, when considering the partial products the middle order take more time for final addition than considering the left and right side of the partial products, So to reduce the middle order partial product delay taking the optimal adder which is having high speed, on considering the BEC-1 adders Which has 3 types of architecture namely EBS, SBS and VBS. Analysis has been made on these adders both manually and experimentally to find out the optimal one in area, delay and power wise and to implement that as the final adder in the high delay path region. The experimental work has been done in typical case 180 nm technology for analyzing area, delay, power for BEC-1 adders. On analysis EBS shows better result manually and experimentally, So putting EBS adder in a unsigned multiplier using DADDA algorithm shows better result.
References
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TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.
Abstract: Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
377 citations
"Design of optimal final adder for p..." refers methods in this paper
...The proposed architecture in [1] has SQBS but in this paper the other two architectures were also taken in to consideration to show which adder is the most efficient by comparative analysis and that efficient adder is used in the multiplier design for faster response....
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23 May 2005
TL;DR: An area efficient square root CSL scheme based on a new first zero detection logic is proposed that witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique.
Abstract: The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 /spl mu/m CMOS technology.
196 citations
TL;DR: Improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile are discussed, yielding a faster multiplier.
Abstract: In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier. >
129 citations
Additional excerpts
...The proposed idea in [2] is taken in to consideration for the delay reduction in high delay path region....
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