Design of prototype scientific CMOS image sensors
07 Aug 2008-Proceedings of SPIE (International Society for Optics and Photonics)-Vol. 7021, pp 702103
TL;DR: In this article, the authors present the design and test results of a prototype 4T CMOS image sensor fabricated in 0.18-µm technology featuring 20 different 6.5 µm pixel pitch designs.
Abstract: We present the design and test results of a prototype 4T CMOS image sensor fabricated in 0.18-µm technology featuring 20 different 6.5 µm pixel pitch designs. We review the measured data which clearly show the impact of the pixel topologies on sensor performance parameters such as conversion gain, read noise, dark current, full well capacity, non-linearity, PRNU, DSNU, image lag, QE and MTF. Read noise of less than 1.5e- rms and peak QE greater than 70%, with microlens, are reported.
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TL;DR: In this article, the authors describe a 55Mpixel 100 frames/sec wide-dynamic-range low-noise CMOS image sensor (CIS) designed for scientific applications.
Abstract: In this paper we describe a 55Mpixel 100 frames/sec wide-dynamic-range low-noise CMOS image sensor (CIS)
designed for scientific applications The sensor has 65μm pitch 5T pixels with pinned photodiodes and integrated
microlenses The 5T pixel architecture enables low noise rolling and global shutter operation The measured peak
quantum efficiency of the sensor is greater than 55% at 550nm, the Nyquist MTF is greater than 04 at 550nm, and the
linear full well capacity is greater than 35ke- The measured rolling and global shutter readout noise are 128e- RMS
and 254e- RMS respectively at 30 f/s and 20°C The pinned photodiode dark current is less than 38pA/cm2 at 20°C
The sensor achieves an intra-scene linear dynamic range in rolling shutter operation of greater than 86dB (20000:1) at
room temperature In global shutter readout the shutter efficiency is greater than 1000:1 with 500nm illumination
61 citations
Cites background from "Design of prototype scientific CMOS..."
...In this paper we present the next key development milestone on our low noise CMOS image sensor (CIS) technology roadmap [2,3,4]....
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TL;DR: In this paper, a pixel-level analog-to-digital conversion (ADC) is implemented at each pixel with a three-transistor structure, where the regenerative latch comparator is divided into an input transistor and the remaining comparator structure shared among the pixels of each column.
Abstract: We present a theoretical analysis, design, and experimental characterization of a CMOS image sensor with pixel-level ΣΔ oversampling analog-to-digital conversion (ADC). The design employs five transistors per-pixel to implement a charge-based ΣΔ ADC at each pixel. In the current design a dynamic regenerative latch comparator is divided into an input transistor, which is contained within each pixel, and the remaining comparator structure shared among the pixels of each column. A charge feedback digital-to-analog converter (DAC) is implemented at each pixel with a three-transistor structure. As opposed to more traditional CMOS image sensors, this image sensor architecture is suitable for implementations in advanced low supply voltage CMOS technologies since its dynamic range is not affected by the reduction of the pixel reset voltage. In addition, similar to the readout methods in low power random access memory designs, this pixel readout architecture does not employ any active amplifiers which allows for low static power operation. Experimental characterization of a prototype fabricated in a 0.35 μm silicided CMOS technology is presented. The estimated power consumption of the fully integrated 128 × 128 imager including decimation filters and I/O interface is 60 nW/pixel at 30 frames per second for 8-bits per-pixel. A peak signal-to-noise ratio of 52 dB and intra-scene dynamic range of 74 dB were measured. The dynamic range was extended to 91 dB through control of the in-pixel DAC supply voltage over the range of 0.8 V-3.3 V.
39 citations
Cites background from "Design of prototype scientific CMOS..."
...[24], [25] and only one of the readings is kept, i....
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01 Jan 2011
TL;DR: This work shows that sigmadelta A/D conversion enables further supply voltage reduction without decreasing the sensor’s sensitivity and the SNR, and demonstrates a sigma-delta image sensor implementation with reduced analog circuit complexity in comparison to earlier efforts.
Abstract: A wide variety of image sensors have been developed
for numerous applications ranging from consumer imaging and cell
phones to space imaging, but in virtually every domain there is an
ever present need for improved image quality and reduced power
consumption. Most CMOS image sensors now include on-chip analog to
digital (A/D) conversion to enable easier integration into a
variety of camera platforms. Nearly all of these employ Nyquist
rate A/D converters, ranging from designs that share one A/D
converter for the entire imaging array to designs that effectively
have a separate ADC for each pixel. In this work we explore the
alternative of employing an oversampling sigma-delta A/D converter
at each pixel. Technology scaling leads to lower supply voltages,
which in turn affects the dynamic range and the signal-to-noise
(SNR) ratio of the image sensor. We show that sigma-delta A/D
conversion enables further supply voltage reduction without
decreasing the sensor‘s sensitivity and the SNR. We also
demonstrate a sigma-delta image sensor implementation with reduced
analog circuit complexity in comparison to earlier efforts.
Furthermore, the sigma-delta modulator is insensitive to the
inevitable electronic noise at the input of the comparator, which
leads to improved light sensitivity. In this work we explore a
specific implementation of the sigma-delta image sensor that may be
capable of reaching the theoretical limit of detecting a single
photon-generated electron during the exposure
time.
15 citations
Additional excerpts
...Other implementations employ dual sampling with adjustable amplifier gain [24], [25], [27]....
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18 Aug 2011
TL;DR: In this paper, the image lag effect in large size 4T pixel for high speed image sensor is simulated and optimized based on 0.13μm CMOS process and the dependence of the potential barrier and the potential pocket on the design and process parameters is studied.
Abstract: In this paper the image lag effect in large size 4T pixel for high speed image sensor is simulated and optimized. The
image lag is mainly caused by the potential barrier and pocket near the transfer gate edge in large size 4T pixel. The
simulation is based on 0.13μm CMOS process. The dependence of the potential barrier and the potential pocket on
design and process parameters is studied. We optimize the parameters, such as offset length between P+ layer and N
layer, N layer doping energy in pinned photodiode (PPD) and TGVT layer doping dose. The simulation results show that
minimum image lag can be obtained at an offset length between P+ and N of 0.3μm, an N layer doping energy of
200KeV and N layer doping dose of 3.5x1012cm-2. The optimizing design effectively improves the charge transfer characteristics of large size 4T pixel and the performance of high speed CMOS image sensor.
12 citations
Cites background from "Design of prototype scientific CMOS..."
...The advantages of four-transistor (4T) pixel [6,7] are extremely attractive for high speed CMOS image sensors....
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TL;DR: In this article, the authors describe a CMOS image sensor with column-parallel delta-sigma (ΔΣ) analog-to-digital converter (ADC), where the unique configuration of the ΔΣ ADC reduces the noise contribution of the readout transistor.
Abstract: We describe a CMOS image sensor with column-parallel delta-sigma (ΔΣ) analog-to-digital converter (ADC). The
design employs three transistor pixels (3T 1 ) where the unique configuration of the ΔΣ ADC reduces the noise
contribution of the readout transistor. A 128 x 128 pixel image sensor prototype is fabricated in 0.35μm TSMC
technology. The reset noise and the offset fixed pattern noise (FPN) are removed in the digital domain. The
measured readout noise is 37.8μV for an exposure time of 33ms. The low readout noise allows an improved low
light response in comparison to other state-of-art designs. The design is suitable for applications demanding
excellent low-light response such as astronomical imaging. The sensor has a measured intra-scene dynamic range
(DR) of 91 dB, and a peak signal-to-noise ratio (SNR) of 54 dB.
8 citations
Cites background from "Design of prototype scientific CMOS..."
...The readout noise is calculated from (1), (3), and (4)....
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References
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08 Dec 2002
TL;DR: Three trends that promise to increase CMOS image sensor system performance are presented: modifications of deep submicron CMOS processes to improve their imaging characteristics, developments that take advantage of these modified deep sub micron processes, and high frame rate sensors and applications to still and video imaging.
Abstract: Three trends that promise to increase CMOS image sensor system performance are presented: (i) modifications of deep submicron CMOS processes to improve their imaging characteristics, (ii) developments that take advantage of these modified deep submicron processes, and (iii) high frame rate sensors and applications to still and video imaging, specifically to extending sensor dynamic range. Recent research on Digital Pixel Sensors and applications of its high frame rate to still and video imaging are discussed.
146 citations
01 Jan 2003
TL;DR: In this paper, the authors investigated the effect of charge transfer noise and lag on the performance of a single poly-photogate-type CMOS APS with a bridging diffusion.
Abstract: This paper reports on the investigation of charge-transfer noise and lag in CMOS image sensors. Noise and lag are analyzed for buried-photodiode CMOS active-pixel-sensor (APS) devices using a simple Monte-Carlo technique. Since the main mechanism of charge-transfer noise involves carrier emission over a barrier, the results are applicable to the soft reset of photodiode-type CMOS APS devices, and charge transfer from a singlepoly-photogate-type CMOS APS with a bridging diffusion. Whereas the literature and conventional wisdom has focused on either (kTC) 1/2 or (kTC/2) 1/2 like behavior, the noise is found to behave like shot noise for both small and large signals. I. Introduction
43 citations
18 Sep 2006
TL;DR: An image sensor with a 2.54mum pixel fabricated in a 0.18mum CMOS technology with 3T pixel with drain-side row-select reduces reset noise by cascoded feedback reset and increases responsivity with common-source readout.
Abstract: An image sensor with a 2.54mum pixel fabricated in a 0.18mum CMOS technology is presented. The 3T pixel with drain-side row-select reduces reset noise by cascoded feedback reset and increases responsivity with common-source readout. The reset noise is 13e- and the responsivity at 550nm is 1.12V/lux-s in source-follower readout mode and 5.6V/lux-s in common-source readout mode
30 citations
"Design of prototype scientific CMOS..." refers background in this paper
...Imager performance parameters such as sensitivity, noise, speed and power have shown substantial improvements [1][2][3]....
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TL;DR: In this article, a high sensitivity and high full well capacity CMOS image sensor using active pixel readout feedback operation with positions of pixel select switch, operation timings and initial bias conditions has been reported.
Abstract: A high sensitivity and high full well capacity CMOS image sensor using active pixel readout feedback operation with positions of pixel select switch, operation timings and initial bias conditions has been reported. 1/3-inch 5.6-μm pixel pitch 800(H) x 600(V) color CMOS image sensors with the switch X set on or under the pixel SF have been fabricated by a 0.18-μm 2-Poly 3-Metal CMOS technology. The comparison of the active pixel readout feedback operation between two CMOS image sensors, which only have the deference of the switch X's position, has performed. As to the result, the switch X set on the pixel SF is favor for the active pixel readout feedback operation to improve the readout gain and the S/N ratio. This CMOS image sensor achieves high readout gain, high conversion gain, low input-referred noise and high full well capacity by the active pixel readout feedback operation.
3 citations
"Design of prototype scientific CMOS..." refers background in this paper
...Imager performance parameters such as sensitivity, noise, speed and power have shown substantial improvements [1][2][3]....
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