scispace - formally typeset

Journal ArticleDOI

Design of quantum cost efficient reversible multiplier using Reed-Muller expressions

01 Jan 2016-International Journal of Computing (Inderscience Publishers (IEL))-Vol. 7, Iss: 3, pp 221-228

TL;DR: This new reversible multiplier was used to design 4-bit reversible multiplier and the results save 16.9% of quantum cost QC, 38.5% of garbage outputs GOs and 10.7% of constant inputs CIs compared to earlier designs.
Abstract: Reversible logic design is one of the emerging trends in recent years as it is good for low power design. A good number of design methods for reversible multipliers were proposed earlier. In this paper, two bit reversible multiplier was designed using Reed-Muller expressions, and this new reversible multiplier was used to design 4-bit reversible multiplier. The results save 16.9% of quantum cost QC, 38.5% of garbage outputs GOs and 10.7% of constant inputs CIs compared to earlier designs. The simulations are done on Xilinx 10.1 and are presented. The methodology is extended for the design of 8-bit and 16-bit multipliers and the reversible logic metrics were presented for different bit lengths.
Topics: Multiplier (economics) (55%), Logic synthesis (54%)
Citations
More filters

Proceedings ArticleDOI
01 Mar 2017-
TL;DR: This work has explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation.
Abstract: Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation. In this work, we have explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation. The proposed reversible multiplier is garbage free design and also optimized in terms of delay and quantum cost with the trade-off in ancillary inputs. The proposed multiplier finds its applications in the design of high-speed, low-power signal processing architectures such as convolution, filtering blocks, FFTs and IFTs.

3 citations


Additional excerpts

  • ...[9] 28 Not mentioned 52 [11] 32 143 28 [12] 30 364 11 [13] 52 152 52 [14]* 46 228 46 [18] 25 216 32 [19] 23 232 22 proposed 25 196 0...

    [...]

  • ...Reed-Muller expressions based multipliers [18] were reported....

    [...]


Book ChapterDOI
01 Jan 2021-
Abstract: Reversible Logic is an emerging field of research which finds its applications in low power computing, Nanotechnology and Quantum Computing. Reversible circuits should have one to one mapping i.e. one input can have only one output so that input vectors can be realized using output vectors. Reversible Circuits require Ancilla(constant inputs) and Garbage Outputs to retain reversibility. An efficient Reversible Circuit can be designed by optimizing their performance parameters. In this paper a \(4 \times 4\) Melior Quantum Multiplier has been proposed which consists of an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs. This proposed multiplier shows an improvement of 21.73% and 18.18% reduction of Ancilla and Garbage Outputs respectively. This multiplier has been implemented in Cadence Virtuoso with average power dissipation of 106.79 nW at 45 nm technology node and used in the implementation of a Linear Phase FIR filter with an average power dissipation of 456.1 nW.

References
More filters

Journal ArticleDOI
TL;DR: Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
Abstract: It is argued that computing machines inevitably involve devices which perform logical functions that do not have a single-valued inverse. This logical irreversibility is associated with physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function. This dissipation serves the purpose of standardizing signals and making them independent of their exact logical history. Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.

3,308 citations


"Design of quantum cost efficient re..." refers background in this paper

  • ...From Landauer (2000) and Ren and Semenov (2011), one can conclude that reversible computation, which dissipates less heat, may be an appreciative logic for the transpiring computing technologies....

    [...]


Journal ArticleDOI
01 Nov 2003-
TL;DR: This paper considers computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.
Abstract: In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation." We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.

465 citations


"Design of quantum cost efficient re..." refers background in this paper

  • ...From thermodynamics point of view, if the computations are carried out reversibly the heat dissipation would be low (Zhirnov et al., 2003)....

    [...]


Journal ArticleDOI
TL;DR: It is shown that the proposed reversible BCD adder has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and garbage outputs with compared to the existing counterparts.
Abstract: This paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as "Copying Circuit" to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all Boolean functions. It also can be used to design optimized adder architectures. This paper also proposes a novel reversible full adder. One of the prominent functionalities of the proposed HNG gate is that it can work singly as a reversible full adder unit. The proposed reversible full adder contains only one gate. We show that its hardware complexity is less than the existing reversible full adders. The proposed full adder is then applied to the design of a reversible 4-bit parallel adder. A reversible Binary Coded Decimal (BCD) adder circuit is also proposed. The proposed circuit can add two 4-bit binary variables and it transforms the result into the appropriate BCD number using efficient error correction modules. We show that the proposed reversible BCD adder has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and garbage outputs with compared to the existing counterparts.

154 citations


"Design of quantum cost efficient re..." refers methods in this paper

  • ...HNG gate (Haghparast and Navi, 2008) is used for implementing the full adder, Peres gate is used to implement half adder and Feynman gate is used to implement the EXOR....

    [...]


Book ChapterDOI
Tsutomu Sasao1Institutions (1)
01 Jan 1993-
TL;DR: This chapter consists of two parts: the first part presents 7 classes of AND-EXOR expressions, and an optimization method for pseudo-ronecker expressions using ternary decision diagrams (TDDs).
Abstract: This chapter consists two parts: the first part presents 7 classes of AND-EXOR expressions:positive polarity Reed-Muller expressions, fixed polarity Reed-Muller expressions, Kronecker expressions, pseudo Reed-Muller expressions, pseudo Kronecker expressions, generalized Reed-Muller expressions and exclusive-or sum-of-products expressions (ESOPs) Relations between these classes are shown The number of products to realize several classes of functions are analyzed Optimization programs for these expressions were developed, and statistical results for arithmetic functions, randomly generated functions, and all the functions of 4 and 5 bariables were obtained The second part presents an optimization method for pseudo-ronecker expressions using ternary decision diagrams (TDDs) The conventional method requires memory of O(3n) to simplify an n-variable expression, and is only practical for functions of up to n = 14 variables The method presented here uses TDDs, and can optimize considerably larger problems Experimental results for up to n = 39 variables are shown

104 citations


"Design of quantum cost efficient re..." refers background in this paper

  • ...(2005), Thaplyal and Sriniva (2006), Shams et al. (2008) and Haghparast et al....

    [...]

  • ...,an) is expanded over the variable ai using following expansions (Sasao, 1993)....

    [...]

  • ...A Boolean function of n-variable f(a1, a2,……,ai,……,an) is expanded over the variable ai using following expansions (Sasao, 1993)....

    [...]


Journal ArticleDOI
Jie Ren1, Vasili K. Semenov1Institutions (1)
TL;DR: A new timing belt clocking scheme is introduced and new circuits based on nSQUID gates with fundamentally low energy dissipation and the ability to operate in irreversible and reversible modes are presented.
Abstract: We continue to develop a new Superconductor Flux Logic (SFL) family based on nSQUID gates with fundamentally low energy dissipation and the ability to operate in irreversible and reversible modes. Prospective computers utilizing the new gates can keep conventional logically irreversible architectures. In this case the energy dissipation is limited by fundamental thermodynamic laws and could be as low as a few kBT s per logic operation. Highly exotic and less practical logically and physically reversible circuit architectures are more attractive for us because they enable a reduction of the specific energy dissipation well below the thermodynamic threshold kBTln2. The reversible option is of interest to us because we can then experimentally demonstrate that all technical mechanisms of the energy dissipation could be cut below the fundamental thermodynamic limit. In other words, we like to set the energy dissipation record for all conventional digital technologies that (if measured in kBT ) is about one million times below the best figures achieved in commercially available semiconductor circuits. Besides, we believe that diving below the thermodynamic threshold would have impressive scientific and philosophical impacts. In the paper we introduce a new timing belt clocking scheme and present new circuits. While we still work with test circuits, some of them contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured at 4 K temperature is already below the thermodynamic threshold. We are confident that we passed through the critical phase of the project and we simply need more time to make more sophisticated circuits. The extremely low energy dissipation converts our circuits into a natural candidate to support circuitry for any sensors operating at milli-Kelvin temperatures.

99 citations


"Design of quantum cost efficient re..." refers background in this paper

  • ...From Landauer (2000) and Ren and Semenov (2011), one can conclude that reversible computation, which dissipates less heat, may be an appreciative logic for the transpiring computing technologies....

    [...]


Network Information
Related Papers (5)
01 Apr 2009, Journal of Circuits, Systems, and Computers

Majid Haghparast, Majid Mohammadi +2 more

01 Jan 2013

H. G. Rangaraju, Aakash Babu Suresh +1 more

01 Jan 2011

Belayet Ali, Hosna Ara Rahman

01 Jan 2008

Masoumeh Shams, Majid Haghparast +1 more

Performance
Metrics
No. of citations received by the Paper in previous years
YearCitations
20211
20171