Design of quantum cost efficient reversible multiplier using Reed-Muller expressions

doi:10.1504/IJCSM.2016.077861

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Design of quantum cost efficient reversible multiplier using Reed-Muller expressions

Journal Article•DOI•

Design of quantum cost efficient reversible multiplier using Reed-Muller expressions

N. Rajeev Pankaj¹, P. Venugopal¹, Prasanthi Mortha¹•Institutions (1)

VIT University¹

01 Jan 2016-International Journal of Computing (Inderscience Publishers (IEL))-Vol. 7, Iss: 3, pp 221-228

TL;DR: This new reversible multiplier was used to design 4-bit reversible multiplier and the results save 16.9% of quantum cost QC, 38.5% of garbage outputs GOs and 10.7% of constant inputs CIs compared to earlier designs.

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Abstract: Reversible logic design is one of the emerging trends in recent years as it is good for low power design. A good number of design methods for reversible multipliers were proposed earlier. In this paper, two bit reversible multiplier was designed using Reed-Muller expressions, and this new reversible multiplier was used to design 4-bit reversible multiplier. The results save 16.9% of quantum cost QC, 38.5% of garbage outputs GOs and 10.7% of constant inputs CIs compared to earlier designs. The simulations are done on Xilinx 10.1 and are presented. The methodology is extended for the design of 8-bit and 16-bit multipliers and the reversible logic metrics were presented for different bit lengths.

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Proceedings Article•DOI•

Design of garbage free reversible multiplier for low power applications

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A. N. Nagamani, S Sharath Kumar, Vinod Kumar Agrawal

01 Mar 2017

TL;DR: This work has explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation.

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Abstract: Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation. In this work, we have explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation. The proposed reversible multiplier is garbage free design and also optimized in terms of delay and quantum cost with the trade-off in ancillary inputs. The proposed multiplier finds its applications in the design of high-speed, low-power signal processing architectures such as convolution, filtering blocks, FFTs and IFTs.

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3 citations

Additional excerpts

...[9] 28 Not mentioned 52 [11] 32 143 28 [12] 30 364 11 [13] 52 152 52 [14]* 46 228 46 [18] 25 216 32 [19] 23 232 22 proposed 25 196 0...
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...Reed-Muller expressions based multipliers [18] were reported....
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Book Chapter•DOI•

Ultra Power Efficient Melior Quantum Multiplier with Reduced Ancilla and Garbage Outputs

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R. Sai Roshan¹, Shaik Nawaz¹, Akshitha Vuppala¹, J.V.R. Ravindra¹•Institutions (1)

Vardhaman College of Engineering¹

01 Jan 2021

TL;DR: In this paper, the authors proposed an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs.

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Abstract: Reversible Logic is an emerging field of research which finds its applications in low power computing, Nanotechnology and Quantum Computing. Reversible circuits should have one to one mapping i.e. one input can have only one output so that input vectors can be realized using output vectors. Reversible Circuits require Ancilla(constant inputs) and Garbage Outputs to retain reversibility. An efficient Reversible Circuit can be designed by optimizing their performance parameters. In this paper a \(4 \times 4\) Melior Quantum Multiplier has been proposed which consists of an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs. This proposed multiplier shows an improvement of 21.73% and 18.18% reduction of Ancilla and Garbage Outputs respectively. This multiplier has been implemented in Cadence Virtuoso with average power dissipation of 106.79 nW at 45 nm technology node and used in the implementation of a Linear Phase FIR filter with an average power dissipation of 456.1 nW.

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1 citations

References

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Proceedings Article•DOI•

Novel Reversible Multiplier Architecture Using Reversible TSG Gate

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Himanshu Thapliyal¹, M. B. Srinivas¹•Institutions (1)

International Institute of Information Technology, Hyderabad¹

08 Mar 2006

TL;DR: It is demonstrated that the proposed multiplier architecture using the TSG gate is much better and optimized, compared to its existing counterparts in literature; in terms of number of reversible gates and garbage outputs.

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Abstract: In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. Recently a 4 * 4 reversible gate called “TSG” is proposed. The most significant aspect of the proposed gate is that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only. This paper proposes a NXN reversible multiplier using TSG gate. It is based on two concepts. The partial products can be generated in parallel with a delay of d using Fredkin gates and thereafter the addition can be reduced to log2N steps by using reversible parallel adder designed from TSG gates. A 4x4 architecture of the proposed reversible multiplier is also designed. It is demonstrated that the proposed multiplier architecture using the TSG gate is much better and optimized, compared to its existing counterparts in literature; in terms of number of reversible gates and garbage outputs. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.

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100 citations

"Design of quantum cost efficient re..." refers methods in this paper

...Table 2 shows the comparison of reversible metrics of the proposed four bit multiplier with the previous designs stated in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al. (2008) and Haghparast et al. (2008) and simulation result is given in Figure 5, where a [3:0] and b [3:0] are…...
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...A good number of design methods for reversible multipliers were proposed in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al. (2008) and Haghparast et al. (2008)....
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Novel Reversible Multiplier Circuit in Nanotechnology

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Masoumeh Shams, Majid Haghparast, Keivan Navi

01 Jan 2008

TL;DR: In this paper, the authors proposed a 4x4 bit reversible multiplier circuit, which is faster and has lower hardware complexity compared to the existing designs in terms of number of gates and number of garbage outputs.

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Abstract: Reversible computation is of the growing interests to power minimization having applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. This paper proposes a novel 4x4 bit reversible Multiplier circuit. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed reversible multiplier is better than the existing counterparts in term of number of gates and number of garbage outputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "MKG". The reversible MKG gate can work singly as a reversible full adder. In this paper we use MKG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit can multiply two 4-bits binary numbers. It can be generalized for NxN bit multiplication.

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79 citations

"Design of quantum cost efficient re..." refers methods in this paper

...…of reversible metrics of the proposed four bit multiplier with the previous designs stated in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al. (2008) and Haghparast et al. (2008) and simulation result is given in Figure 5, where a [3:0] and b [3:0] are multiplicand and…...
[...]
...A good number of design methods for reversible multipliers were proposed in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al. (2008) and Haghparast et al. (2008)....
[...]

Proceedings Article•DOI•

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

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Mathias Soeken¹, Robert Wille¹, Rolf Drechsler¹•Institutions (1)

University of Bremen¹

01 Dec 2010-Intelligent Decision Technologies

TL;DR: This paper proposes an alternative that additionally makes use of positive Davio and negative Davio decomposition and shows that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits.

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Abstract: Synthesis of reversible circuits is an important research area providing the basis for a design flow of this emerging technology Recently, in the development of scalable synthesis approaches a significant step forward has been made by a hierarchical method in combination with Shannon decom-position However, this approach leads to circuits with high costs In this paper, we propose an alternative that additionally makes use of positive Davio and negative Davio decomposition We show that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits Using the proposed approach, on average the number of lines can be reduced by 22%, the number of gates by 22%, and the quantum cost by 32% In the best case, even reductions of more than 60% are possible

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39 citations

"Design of quantum cost efficient re..." refers methods in this paper

...Table 2 shows the comparison of reversible metrics of the proposed four bit multiplier with the previous designs stated in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al....
[...]
...A good number of design methods for reversible multipliers were proposed in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al....
[...]
...In Hu et al. (2006), Takahashi and Hirayama (2009), Pang et al. (2011), Jing and Muzio (2007) and Soeken et al. (2010), the authors proposed different algorithms to represent the output vector of the design using Reed-Muller expressions....
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Proceedings Article•

A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.

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Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia

01 Jan 2005

33 citations

"Design of quantum cost efficient re..." refers methods in this paper

...Table 2 shows the comparison of reversible metrics of the proposed four bit multiplier with the previous designs stated in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al. (2008) and Haghparast et al. (2008) and simulation result is given in Figure 5, where a [3:0] and b [3:0] are…...
[...]
...A good number of design methods for reversible multipliers were proposed in Thaplyal et al. (2005), Thaplyal and Sriniva (2006), Shams et al. (2008) and Haghparast et al. (2008)....
[...]

Journal Article•DOI•

Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions

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Mozammel H. A. Khan¹•Institutions (1)

East West University¹

01 Nov 2014-IEEE Transactions on Very Large Scale Integration Systems

TL;DR: This paper proposes a novel approach of designing synchronous sequential circuits directly from reversible gates using pseudo Reed-Muller expressions representing the state transition and the output functions of the circuit.

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Abstract: Reversible logic has become very promising for low-power design using emerging computing technologies. A number of good works have been reported on reversible combinational circuit design. However, only a few works reported on the design of reversible latches and flip-flops on the top of reversible combinational gates and suggested that sequential circuits be built by replacing the latches and flip-flops and associated combinational gates of the traditional irreversible designs by their reversible counter parts. This replacement technique is not very promising, because it leads to high quantum cost and garbage outputs. In this paper, we propose a novel approach of designing synchronous sequential circuits directly from reversible gates using pseudo Reed-Muller expressions representing the state transition and the output functions of the circuit. We present designs of arbitrary synchronous sequential circuit as well as practically important sequential circuits such as counters and registers. It is found that our direct designs save 1.54%-49.09% quantum cost and 51.43%-81.82% garbage outputs than the replacement design approach suggested earlier.

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23 citations

"Design of quantum cost efficient re..." refers background in this paper

...The Feynman gate, the Toffoli gate and the Peres gate are some of the basic reversible gates (Khan, 2014)....
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...Khan (2014) stated that pseudo Reed-Muller (PSDRM) expression is more generalised class of Reed-Muller expression and the PSDRM-based reversible design synthesis is more effective....
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...If a coefficient is one, only then the associated product term appears in the final expression (Khan, 2014)....
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...The QC of 1 1 and 2 2 gates is one and these gates are primitive gates which are technologically realisable (Khan, 2014)....
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