Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic
Summary (3 min read)
Introduction
- This has forced the supply voltage (Vdd) to remain relatively constant across CMOS technology generations, causing power density to increase with transistor density and thus limiting the performance benefits of transistor scaling [1].
- In order to arrive at the proposed methodology, Section II begins this paper by developing a general model for relay logic delay and energy that is calibrated to experimental data.
II. LOGIC RELAY ENERGY–DELAY MODEL
- The principle and analytical models for MEM relay operation are described to provide the necessary 0018-9383/$26.00 © 2010 IEEE background for a subsequent discussion of design optimization and scaling.
- A metallic channel electrode is attached underneath the gate electrode via an intermediary gate dielectric layer.
- In the case of a 4T relay, although the device turns on when |Vgb| increases above Vpi, it turns off when |Vgb| is lowered below the “release voltage” (Vrl).
- The hysteretic switching behavior (Vrl < Vpi) occurs for “pull-in-mode” operation (wherein Felec remains larger than Fspring for values of Vrl < |Vgb| < Vpi when the channel is in contact with the source/drain electrodes) and is exacerbated by surface adhesion force (FA) in the contact regions.
- The as- fabricated air gap in the contacting region (gd) can be made to be smaller than the as-fabricated air gap in the actuation region (g) to reduce the hysteresis voltage.
A. Switching Voltages
- The relay switching voltages can be derived by balancing the electrostatic force against the spring restoring force.
- The first prototype 4T relay design reported in [10] suffers from gate dielectric charging issues, leading to unwanted parasitic actuation effects as well as undesirable influence on gate switching voltages and pull-in time.
- This is because the mechanical design and models of energy and performance for 4T and 3T relays are essentially identical.
- This is within 2× of the ∼0.2-μN FA value obtained via atomic force microscopy measurements [19].
B. Turn-On Delay
- For RF relays which employ micrometer-scale actuation gaps, Q is limited by squeeze-film damping.
- It has been shown that Q decreases linearly with beam thickness and is independent of the beam width and beam length [21], [22].
- In fact, it may be preferable to avoid high-Q relay designs to minimize non-ideal switching effects such as contact bounce and long settling time.
C. Switching Energy
- The energy consumed in switching a relay is supplied by the voltage source which charges/discharges capacitances.
- By using the calibrated delay and energy models, the switching voltages, delay, and energy for relays with various design parameters can be predicted.
- These, in turn, can be used for relay circuit design optimization.
III. RELAY ENERGY–DELAY OPTIMIZATION
- Since the switching delay of a relay is dominated by its mechanical delay rather than its electrical delay, an optimized relay-based circuit design should utilize complex gates [8] such that all the relays move simultaneously and only one mechanical delay is incurred per operation.
- In optimizing a relay circuit design, it is important to note that, as for a CMOS circuit design [23]–[28], energy and delay are traded off by adjusting various device design parameters.
- The energy-delay tradeoff is optimized essentially by solving the following constrained optimization problem for the N-relay complex gate: Minimize : tdelay ∼= α √ meff keff ( gd g )γ ( Vdd Vpi − χ )−β.
- In a complex gate, not all the nodes (i.e., capacitances) switch with equal probability; therefore the authors can generalize the circuit to have an average activity.
A. Sensitivity Analysis
- CMOS integrated circuit optimization utilizing energy-delay sensitivity analysis has been described extensively in [23]–[28], so only the key concepts are briefly reviewed here.
- 1) Sensitivity to Supply Voltage (Vdd): As Vdd increases, the switching delay decreases because the electrostatic force increases, but the switching energy increases.
- Where tdelay and Es are the delay and energy, respectively, at a given Vdd and Vnorm = βVdd/(Vdd − χVpi).
B. Relay Design Optimization
- An optimized relay design is reached by balancing the various sensitivities to the design variables.
- As a result, the optimal fixed-to-area-dependent capacitance ratio is less than one, as shown in Fig. 14.6 5) Relay Design Optimization Procedure:.
- From the results of the sensitivity analysis, the following simple relay design optimization procedure (illustrated in Fig. 16) can be established.
- 4) Finally, the optimal beam length is calculated to result in the optimal Vpi.
- To provide a concrete example, this procedure is applied to optimize the design of a 5-μm-wide relay (with the parameters shown in Table I) for a nominal switching energy Es = 2 pJ and an average fixed capacitance CL ranging from 10 to 100 fF.
C. Energy-Efficiency Limit
- For ultra-low-power electronics applications such as wireless sensor networks, switching energy [32] rather than speed is the primary concern.
- The minimum switching energy for relays is dictated by the need for the spring restoring force to overcome the surface adhesion energy (Γ) in the ON state, in order to break physical contact 0.5keffg 2 d ≥ Γ. (24).
- In other words, the minimum spring stiffness is keff = 2Γ/g2d.
- Of course, the switching energy will be higher for any realistic relay design since operation with Vrl = 0 V and Vdd = Vpi provides for no noise margin and thus would be highly impractical.
IV. SCALING IMPLICATIONS
- Relay miniaturization is desirable for improved device density and reduced operating voltage.
- Surface adhesion energy and, therefore, the minimum relay switching energy improve by S2.
- Since the total capacitance is reduced by S and the switching energy improves by S2, the supply voltage can be scaled down by S0.5.
- Given that relay circuits would be used for applications with clock frequencies up to ∼100 MHz, it is of practical interest to compare them against subthreshold-CMOS circuits (operated with Vdd < VT ), which are designed to operate with very low power consumption [6], [32].
V. CONCLUSION
- Circuit-level energy-performance analysis is necessary to evaluate the promise of any new device technology for potentially overcoming the energy-efficiency limitations of CMOS technology.
- For a given contact dimple gap thickness, the optimal dimple-gap thickness to actuation-gap thickness ratio is roughly 0.7, meaning that pull-in operation is preferred for energy-efficient relay design.
- Specifically, a lower bound for Vcpi can be derived by modeling the movable plate as a beam pinned at the two contact dimple regions.
- G. M. Rebeiz, RF MEMS, Theory, Design and Technology.
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Cites background or methods from "Design, Optimization, and Scaling o..."
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Frequently Asked Questions (19)
Q2. What are the future works mentioned in the paper "Design, optimization, and scaling of mem relays for ultra-low-power digital logic" ?
M. A. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, “ Scaling, power, and the future of CMOS, ” in IEDM Tech. In 1992, she joined the Xerox Palo Alto Research Center, Palo Alto, CA, as a Member of the research staff, where she worked on the research and development of polycrystalline-silicon thin-film transistor technologies for high-performance flat-panel displays.
Q3. What is the way to optimize a relay?
Much like transistor scaling, relay miniaturization leads to dramatic improvements in density (for lower cost perfunction), switching delay (for higher performance), and energy efficiency.
Q4. What is the optimal dimple gap thickness to actuation gap ratio?
For a given contact dimple gap thickness, the optimal dimple-gap thickness to actuation-gap thickness ratio is roughly 0.7, meaning that pull-in operation is preferred for energy-efficient relay design.
Q5. How many T relays have been demonstrated using conventional surface micromachining processes?
Using ANSYS, γf and γt are found to be 3.66 and14T relays have been demonstrated using conventional surface micromachining processes [10].
Q6. How many beams are supported to the substrate?
The gate electrode is supported by four suspended beams (with an effective spring constant keff ) anchored to the substrate at four corners.
Q7. What is the optimum gate capacitance for a CMOS circuit?
In fact, the International Technology Roadmap for Semiconductors (ITRS) [40] predicts that the gate capacitance will only decrease by ∼2.5× as the transistor physical gate length is scaled from 38 to 7.4 nm.
Q8. What is the effect of the actuation area on the relay design?
This means that relay designs with lower beam stiffness, smaller contact dimple gap thickness, and therefore lower actuation area and supply voltage are feasible if a smaller contact dimple area is utilized.
Q9. What is the effect of surface-related energy loss mechanisms on tdelay?
the quality factor of nanometer-scale logic relays will be dominated by surface-related energy-loss mechanisms, due to their relatively large surface-to-volume ratio.
Q10. Why is the minimum device width scaling so slow?
due to increasing variability, the minimum device width has been scaling relatively slowly and leading to minimal reduction in CMOS.
Q11. How many times would the physical gate length be scaled down to below 5 nm?
(28)Assuming ideal MOSFET scaling and constant operating temperature, Vddopt,MOS remains relatively constant, and hence, the minimum energy of CMOS scales linearly by the factor S. Based on Fig. 21, the physical gate length would need to be scaled down by approximately 20 times (i.e., to below 5 nm) to match the minimum energy potentially achievable with relays.
Q12. What is the optimum supply voltage for a CMOS circuit?
As derived in [6] and [32], the optimum supply voltage is proportional to the thermal voltageVddopt,MOS ∝ n × kBT/q (27)where n ≈ 1.2 is the subthreshold factor [6], [32].
Q13. Where is the optimal beam length for a low-Q relay?
From (23), for a low-Q relay with κ ≈ −0.34 and Vnorm ≈ 1.17−1.29, the optimal Cnorm ranges from 0.74 to 0.13; for a high-Q relay with κ ≈ −0.4 and Vnorm ≈ 1.17−1.29, the optimal Cnorm ranges from 0.97 to 0.27.7
Q14. How can FA be extracted from the measurements of Vpi and Vrl?
FA can be extracted from the measurementsof Vpi and Vrl for devices of various beam lengths, according to the following equation [derived from (1)]:V 2rl = 27 4 gd g( 1 − gdg)2 V 2pi −2(g − gd)2 εoA FA. (3)FA is extracted to be 0.45 μN on average for TiO2-coated tungsten electrodes with a contact dimple area (Ad) of 2 × 10 μm2, as shown in Fig.
Q15. What is the effective spring constant of the movable structure?
Vrl =√ 2(keffgd − FA)(g − gd)2εoA (1)where keff is the effective spring constant of the movable structure and A is the actuation area (≈ LA × WA, ignoring release etch holes).
Q16. What is the optimal supply voltage of a 32-bit adder?
As discussed in [39], due to this effect, the optimal supplyvoltage of a 32-bit adder increases from ∼0.25 to ∼0.33 V from the 65- to 32-nm technology nodes.
Q17. How is the energy efficiency of a relay optimized?
As will be derived in the following section, the energy efficiency of a relay is optimized by operating it in pull-in mode, i.e., designing it such that gd > g/3.
Q18. What is the effect of a squeeze film on the actuation gap?
In contrast, for scaled logic relays with actuation gaps approaching 10 nm, i.e., less than the mean free path of an air molecule, squeeze-film damping will be negligible.
Q19. What is the voltage between the movable gate electrode and the fixed body electrode?
The voltage applied between the movable gate electrode and the fixed body electrode determines whether current can flow between the source and drain electrodes.