Proceedings ArticleDOI
Design Space Exploration of RISC Architectures using retargetability
Harsh Arora,Abhinav Gupta,Raunak Singhai,Diptanshu Purwar +3 more
- pp 1-3
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TLDR
This paper describes how to model a processor in an Architecture Description Language (ADL), how to generate tools to perform DSE, and finally how to evaluate performance.Abstract:
Processor development is done in stages. It is a safe bet if we start by modeling the processor at a high level of abstraction, perform refinements at high level, and when we are satisfied by the performance, go into manufacturing. The process of refinement is done by evaluating the design criteria. This process generally goes through a cycle that can be described as Design Space Exploration (DSE). In this paper, we describe how to model a processor in an Architecture Description Language (ADL), how to generate tools to perform DSE, and finally how to evaluate performance.read more
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Proceedings ArticleDOI
Design & analysis of 16 bit RISC processor using low power pipelining
TL;DR: A 16 bit low power pipelined RISC processor is proposed by us in this paper, the RISC Processor consists of the block mainly ALU, Universal shift register and Barrel Shifter.
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Journal ArticleDOI
The ArchC architecture description language and tools
TL;DR: This paper has used ArchC to synthesize both functional and cycle-based simulators for the MIPS and Intel 8051 processors, as well as functional models of architectures like SPARC V8, TMS320C62x, XScale and PowerPC.
Journal ArticleDOI
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs
TL;DR: The heart of this approach lies in the ability to automatically generate a software toolkit that includes an architecture-sensitive compiler, a cycle-accurate simulator, assembler, debugger, and verification/validation tools.