Developing Variation Aware Simulation Tools, Models, and Designs for STT-RAM
25 Jan 2018-
TL;DR: This work introduces a new member of NVSim family – NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption and proposes two possible SHE-RAM designs from the aspects of two different write access operations.
Abstract: DEVELOPING VARIATION AWARE SIMULATION TOOLS, MODELS, AND DESIGNS
FOR STT-RAM
Enes Eken, PhD
University of Pittsburgh, 2017
In recent years, we have been witnessing the rise of spin-transfer torque random access memory
(STT-RAM) technology. There are a couple of reasons which explain why STT-RAM has attracted
a great deal of attention. Although conventional memory technologies like SRAM, DRAM
and Flash memories are commonly used in the modern computer industry, they have major shortcomings,
such as high leakage current, high power consumption and volatility. Although these
drawbacks could have been overlooked in the past, they have become major concerns. Its characteristics,
including low-power consumption, fast read-write access time and non-volatility make
STT-RAM a promising candidate to solve the problems of other memory technologies. However,
like all other memory technologies, STT-RAM has some problems such as long switching time and
large programming energy of Magnetic Tunneling Junction (MTJ) which are waiting to be solved.
In order to solve these long switching time and large programming energy problems, Spin-Hall
Effect (SHE) assisted STT-RAM structure (SHE-RAM) has been recently invented. In this work, I
propose two possible SHE-RAM designs from the aspects of two different write access operations,
namely, High Density SHE-RAM and Disturbance Free SHE-RAM, respectively. In addition to
the SHE-RAM designs, I will also propose a simulation tool for STT-RAMs. As an early-stage
modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory
technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. I will
introduce a new member of NVSim family – NVSim-VXs, which enables statistical simulation of
STT-RAM for write performance, errors, and energy consumption.
Citations
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01 Jan 2012
TL;DR: In this article, two 3D stacking structures built upon bipolar RRAM crossbars are proposed to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance.
Abstract: For its simple structure, high density, and good scalability, the resistive random access memory (RRAM) has emerged as one of the promising candidates for large data storage in computing systems. Moreover, building up RRAM in a 3-D stacking structure further boosts its advantage in array density. Conventionally, multiple bipolar RRAM layers are piled up vertically separated with isolation material to prevent signal interference between the adjacent memory layers. The process of the isolation material increases the fabrication cost and brings in the potential reliability issue. To alleviate the situation, we introduce two novel 3-D stacking structures built upon bipolar RRAM crossbars that eliminate the isolation layers. The bigroup operation scheme dedicated for the proposed designs to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance is also presented. Our simulation results show that the proposed designs can increase the capacity of a memory island to 8K-bits (i.e., eight layers of 32 × 32 crossbar arrays) while maintaining the sense margin in the worst case configuration greater than 20% of the maximal sensing voltage.
22 citations
01 Jan 2019
TL;DR: The Digital Commons as discussed by the authors is part of the Business Administration, Management, and Operations Commons, Business and Corporate Communications Commons, Entrepreneurial and Small Business Operations, Organizational Behavior and Theory Commons, Organization Development Commons, Technology and Innovation Commons, and the Women's Studies Commons.
Abstract: Follow this and additional works at: https://digitalcommons.brandman.edu/edd_dissertations Part of the Business Administration, Management, and Operations Commons, Business and Corporate Communications Commons, Entrepreneurial and Small Business Operations Commons, Organizational Behavior and Theory Commons, Organization Development Commons, Technology and Innovation Commons, and the Women's Studies Commons
4 citations
Cites background from "Developing Variation Aware Simulati..."
...Other studies discussed women in small business startups, especially African American and other 14 minority women (Devarakonda, 2015; Eken, 2017; Gaines, 2011; Lindell, 2016; Muron, 2017)....
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...Some looked at women-founded startups (Devarakonda, 2015; Eken, 2017; Gaines, 2011; Lindell, 2016; Muron, 2017)....
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Proceedings Article•
01 Jan 2012
TL;DR: This work systematically analyzes the variation sources of MLC STT-RAM designs and their impacts on the reliability of the read and write operations, and discusses the optimal device parameters of the MLC MTJ for the minimization of the operation error rate of the SOTA cells from statistical design perspective.
Abstract: Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ) devices. In parallel with these efforts, the continuous increasing of tunnel magneto-resistance(TMR) ratio of the MTJ inspires the development of multi-level cell (MLC) STT-RAM, which allows multiple data bits be stored in a single memory cell. Two types of MLC STT-RAM cells, namely, parallel MLC and series MLC, were also proposed. The storage margin of a MLC STT-RAM cell, i.e., the distinction between the lowest and highest resistance states, is partitioned into multiple segments for multi-level data representation. As a result, the performance and reliability of MLC STT-RAM cells become more sensitive to the MOS and MTJ device variations and the thermal-induced randomness of MTJ switching. In this work, we systematically analyze the variation sources of MLC STT-RAM designs and their impacts on the reliability of the read and write operations. On top of that, we also discuss the optimal device parameters of the MLC MTJ for the minimization of the operation error rate of the MLC STT-RAM cells from statistical design perspective. Our simulation results show that under the current available technology, series MLC STT-RAM demonstrates overwhelming benefits in the read and write reliability compared to parallel MLC STT-RAM and could potentially satisfy the requirement of commercial practices.
2 citations
References
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TL;DR: NVSim is developed, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash and is expected to help boost architecture-level NVM-related studies.
Abstract: Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.
1,100 citations
"Developing Variation Aware Simulati..." refers methods in this paper
...2 Basics of NVSim NVSim is a widely used open source simulation framework for circuit-level modeling of emerging nonvolatile memories like STT-RAM, ReRAM, PCM, etc [6]....
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...released the most widely used STT-RAM block-level model, namely, NVSim [6], which can support the design parameter extraction of not only STT-RAM but also ReRAM and PCM....
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IBM1
TL;DR: In this paper, the authors examined the consequence of spin-current-induced angular momentum deposition in a monodomain Stoner-Wohlfarth magnetic body using the Landau-Lifshitz-Gilbert equation with a phenomenological damping coefficient.
Abstract: I examined the consequence of a spin-current-induced angular momentum deposition in a monodomain Stoner-Wohlfarth magnetic body. The magnetic dynamics of the particle are modeled using the Landau-Lifshitz-Gilbert equation with a phenomenological damping coefficient $\ensuremath{\alpha}.$ Two magnetic potential landscapes are studied in detail: One uniaxial, the other uniaxial in combination with an easy-plane potential term that could be used to model a thin-film geometry with demagnetization. Quantitative predictions are obtained for comparison with experiments.
1,075 citations
"Developing Variation Aware Simulati..." refers background or methods in this paper
...HereHθ andHφ are the net effective fields containing biaxial anisotropy, easyplane anisotropy[21]....
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...The magnetization dynamics of the MTJ free layer in SHE-RAM design can be modeled by solving the Landau-Lifshitz-Gilber (LLG) equation [21] with SHE current modification [24] as:...
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...Langevin random thermal field [17], and STT field [21] for θ and φ components....
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06 Mar 2009
TL;DR: This paper stacks MRAM-based L2 caches directly atop CMPs and compares it against SRAM counterparts in terms of performance and energy, and proposes two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache.
Abstract: Magnetic random access memory (MRAM) is a promising memory technology, which has fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it becomes feasible and cost-efficient to stack MRAM atop conventional chip multiprocessors (CMPs). However, one disadvantage of MRAM is its long write latency and its high write energy. In this paper, we first stackMRAM-based L2 caches directly atop CMPs and compare it against SRAM counterparts in terms of performance and energy. We observe that the direct MRAM stacking might harm the chip performance due to the aforementioned long write latency and high write energy. To solve this problem, we then propose two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache. The simulation result shows that our optimized MRAM L2 cache improves performance by 4.91% and reduces power by 73.5%compared to the conventional SRAM L2 cache with the similar area.
459 citations
"Developing Variation Aware Simulati..." refers background in this paper
...Although STT-RAM features many attractive characteristics like non-volatility, low standby power, and high cell density [20, 31, 36], it also has many drawbacks such as long programming latency and high programming energy etc....
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IBM1
TL;DR: A novel methodology based on an efficient form of importance sampling, mixture importance sampling is proposed for statistical SRAM design and analysis, which is comprehensive, computationally efficient and in excellent agreement with standard Monte Carlo techniques.
Abstract: In this paper, we propose a novel methodology for statistical SRAM design and analysis. It relies on an efficient form of importance sampling, mixture importance sampling. The method is comprehensive, computationally efficient and the results are in excellent agreement with those obtained via standard Monte Carlo techniques. All this comes at significant gains in speed and accuracy, with speedup of more than 100/spl times/ compared to regular Monte Carlo. To the best of our knowledge, this is the first time such a methodology is applied to the analysis of SRAM designs.
371 citations
"Developing Variation Aware Simulati..." refers methods in this paper
...In our work, we introduce the mixture importance sampling technique in NVSim-VXs to reduce the write error rate calculation cost as [13, 14]:...
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02 Nov 2009
TL;DR: Results indicate that EWT is an effective and practical scheme to improve the energy efficiency of a STT-RAM cache, and up to 80% of write energy reduction can be achieved through EWT.
Abstract: The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high. In this paper, we propose Early Write Termination (EWT), a novel technique to significantly reduce write energy with no performance penalty. EWT can be implemented with low complexity and low energy overhead. Our evaluation shows that up to 80% of write energy reduction can be achieved through EWT, resulting 33% less total energy consumption, and 34% reduction in ED2. These results indicate that EWT is an effective and practical scheme to improve the energy efficiency of a STT-RAM cache.
349 citations
"Developing Variation Aware Simulati..." refers background or methods in this paper
..., dynamically adjusting the write time of the MTJ to assure the completion of the write like early termination technology [36], may be critical in the MLC STT-RAM design based on the biaxial MTJ for energy reduction and reliability enhancement....
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...Although STT-RAM features many attractive characteristics like non-volatility, low standby power, and high cell density [20, 31, 36], it also has many drawbacks such as long programming latency and high programming energy etc....
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...However, in real applications, the energy consumption of the switchings from ‘0’ to ‘1’ or ‘2’ can be further reduced when early-termination technique is applied [36], where the switching current is timely removed once the MTJ switching completes....
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