Development of CRC block onn FPGA for Zigbee standard

TLDR: The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i to characterize the CRC block behavior which is simulated, synthesized and successfully implemented on Spartan3E XC3S500E FPGA.

Abstract: CRC (Cyclic Redundanncy Check) block was developed on FPGA (Field Programmable Gate Array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee Standard. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i. The Verilog code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Spartan3E XC3S500E FPGA. Here, the simulation and measurement results are also presented to verify the functionality of the CRC block. The data rate of CRC block is 250 kbps.