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Proceedings ArticleDOI

Development of Low-Cost Silicon BiCMOS Technology for RF Applications

TL;DR: In this article, the authors presented the device design, process development and optimization of diffusion bipolar junction transistor (BJT), for the first time in India, for analog and RF applications.
Abstract: It is well known that combining the benefits of bipolar and CMOS (Complementary Metal Oxide Semiconductor) devices in BiCMOS technology, one can achieve better speed and power-density in microelectronic circuitry. In this work, we present the device design, process development and optimization of diffusion bipolar junction transistor (BJT), for the first time in India, for analog and RF applications. The baseline 180nm CMOS process of Semi-Conductor Lab (SCL) at Chandigarh is used to develop the BiCMOS process. All the TCAD simulations are calibrated with the measured data of baseline BJT from 180nm CMOS process with two different process splits. Calibrated simulations of our proposed silicon BJT show current gain > 90 and current driving capacity > 10 mA. The breakdown voltage of the transistor is above 25 V (BVCB0) with cut-off frequency (f T ) and maximum oscillation frequency (f max ) more than 5 GHz and 3 GHz, respectively.
Citations
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Proceedings ArticleDOI
11 Dec 2022
TL;DR: A low-cost BiCMOS process integrable with Semi-Conductor Laboratory's (SCL's) 180 nm CMOS process flow is developed for designing indigenous application-specific integrated circuits (ASICs) for Indian regional satellite navigation system NavIC as discussed by the authors .
Abstract: A low-cost BiCMOS process integrable with Semi-Conductor Laboratory's (SCL's) 180 nm CMOS process flow is developed for designing indigenous application-specific integrated circuits (ASICs) for Indian regional satellite navigation system NavIC. The process is optimized for realizing high frequency (HF) as well as high voltage (HV) double polysilicon bipolar junction transistors and is robust to process variations. The designed HF device has fT/fmax~ 29/50 GHz, and the HV device has a breakdown voltage of ~10 V.
References
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Book
Yuan Taur1, Tak H. Ning1
01 Jan 2016
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

2,680 citations

DOI
20 Sep 2004

1,387 citations


"Development of Low-Cost Silicon BiC..." refers background in this paper

  • ...Driven by this motivation, Europe got ahead of the RF ITRS roadmap [3] with highly ambitious projects like DOTFIVE [4] and DOTSEVEN [5], [6] resulting in fmax close to 0....

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Book
31 Dec 2002
TL;DR: In this paper, a Si bipolar transistor was used to achieve respectable Si bipolar performance down to liquid-nitrogen temperature (LNT = 77 K), but it is unlikely that conventional designed Si bipolar technology will offer performance attractive enough to make it a serious contender to CMOS, a proven technology for cryogenic applications.
Abstract: Silicon (Si) bipolar transistor technology, despite its desirable features of fast switching speed, high transconductance, and excellent current-drive capability at room temperature (RT = 300 K), is often viewed as unsuitable for the cryogenic environment because its current gain (β = Jc/JB), frequency response, and circuit speed typically degrade strongly with cooling [1,2]. Recent evidence [3–6] indicates, however, that careful profile design can be used to achieve respectable Si bipolar performance down to liquid-nitrogen temperature (LNT = 77 K). Even with these improvements, however, it is unlikely that conventionally designed Si bipolar technology will offer performance attractive enough to make it a serious contender to CMOS, a proven technology for cryogenic applications.

328 citations

Patent
21 Sep 2011
TL;DR: In this paper, a SiGe HBT is disclosed, which consists of a collector region consisting of a first ion implantation region in an active area as well as second and third implantation regions respectively at bottom of field oxide regions.
Abstract: A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.

296 citations

Journal ArticleDOI
TL;DR: In this article, the first integrated circuits in the silicon:germanium materials system were presented, with the first IC components being SiGe HBT based 1 Ghz, 12 bit, digital to analog converters.
Abstract: Recent advances in thin film growth techniques, notably the maturation of low temperature silicon epitaxy, have enabled the routine fabrication of highly controlled dopant and silicon:germanium alloy profiles. These capabilities, combined with refinements in heterojunction bipolar transistor designs, have led to the first integrated circuits in the silicon:germanium materials system. Utilizing a commercial (Leybold-AG) UHVCVD tool for SiGe epitaxy on a standard 8" CMOS line, medium scale integration has been achieved, with the first IC components being SiGe HBT based 1 Ghz, 12 bit, digital to analog converters.

220 citations


"Development of Low-Cost Silicon BiC..." refers background in this paper

  • ...First, we illustrate our systematic calibration approach of the simulations using the measured data of the baseline BJT of SCL’s 180nm CMOS process....

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  • ...I. INTRODUCTION Soon after the replacement of bipolar logic with Complementary Metal Oxide Semiconductor (CMOS) logic due to excessive heat generation in integrated bipolar chips, bipolar transistors were used in RF and mixed signal applications, where speed is preferred over low-power operation [1], [2]....

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  • ...It is well known that at any given technology node, the maximum speed and operating frequency of the bipolar transistor is higher than CMOS [7] and due to the low noise and relatively higher power capacity, BJTs are preferred over CMOS devices in certain analog and RF applications....

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  • ...Simulations performed in this work are calibrated against the measurements of baseline BJT of SCL’s 180nm CMOS process....

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  • ...The 180nm CMOS process of SemiConductor Lab (SCL), India, is used as the baseline process....

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