Development of sequential build-up multilayer printed wiring boards in Japan
TL;DR: Activity is still high in the development of embedded passive technology, which will equip printed wiring boards with the functions of passive components resistance, capacitance and inductance - as well as the conventional interconnection functions of conductors between components.
Abstract: Printed Wiring Boards (PWB) made by Sequential Build-Up (SBU) processes have found a wide application in semiconductor packaging substrates and system in package substrates, besides usage as a conventional printed wiring board. Its capability for high density circuits can contain multi-functional electronic circuits within a small surface area and can achieve light weight and low-profile products with improved electric characteristics. A number of processes and materials were developed and are used for each application in each electronic product. The advancement of printed wiring boards is expected to continue, driven by the requirements from electronic products. Technical development activities are needed to satisfy these requirements. Activities are still high in the development of embedded passive technology, which will equip printed wiring boards with the functions of passive components resistance (R), capacitance (C) and inductance (L) - as well as the conventional interconnection functions of conductors between components. This technology will dramatically change the structure of printed wiring boards and complicate the fabrication processes. Material development will be a key issue in the case of embedded resistors and capacitors.
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TL;DR: In this article, an organic additive, Diazine Black (DB), was employed as a leveler for microvia filling using copper electroplating, which is a derivative of Janus Green B (JGB), which is used for copper fill of submicron or micron circuit metallization in electronic products.
109 citations
TL;DR: In this paper, the authors explored the mechanism of microvia filling by copper electroplating using a printed circuit board (PCB) with a specific pattern design, and found that bottom-up filling stemmed from the sidewall growth of the microvia, increasing the surface coverage of an accelerator; the convection-dependent adsorption of additives, leading to different copper deposition rates on the outer and inner copper layers.
97 citations
TL;DR: In this paper, a pre-treatment of the microvia was carried out using a plating bath containing a suppressor and a leveler without an accelerator and the required accelerator was adsorbed onto the copper seed layer in a predipping bath before the filling plating.
Abstract: Microvia filling by copper electroplating was carried out using a plating bath containing a suppressor and a leveler without an accelerator. The required accelerator was adsorbed onto the copper seed layer of the microvia in a predipping bath before the filling plating. This pretreatment is similar to the self-assembled monolayer of thiol molecules that forms on a copper surface. The suppressor was poly(ethylene glycol) (PEG), and five levelers, namely, Janus green B, diazine black, methylene violet, safranine O, and Alcian blue, were employed to screen for the best plating formula suitable for a plating process in which no accelerator was present in the plating solution. The thiol molecule employed in this work was 3-mercapto-1-propanesulfonate (MPS). The electrochemical behaviors of various plating formulas were characterized using a galvanostatic measurement on a copper electrode at different rotating speeds. Results indicated that the MPS adlayer is transferable onto the surface of the copper deposit and can be displaced by the PEG-C1-leveler. The displacement rate depends on the molecular structure of the added leveler. This plating process has the potential to greatly reduce the plating time of microvia filling.
94 citations
TL;DR: In this paper, cylindrical, V-and X-shaped through holes were formed by laser drilling on a printed circuit board to evaluate the filling capability of two copper plating formulas.
Abstract: Through holes (THs) with different shapes were formed by laser drilling on a printed circuit board to evaluate the filling capability of two copper plating formulas. The shapes of these THs were cylindrical, V- and X-shaped. Two copper plating formulas, accelerator-free formula (AFF) and accelerator-containing formula (ACF), were employed in this work. The AFF contained only one organic additive and the ACF was composed of multiorganic additives. The electrochemical characteristics of the AFF were investigated by cyclic voltammetry, which could be utilized to explain the results of filling plating. The plating results showed that the cylindrical TH could be fully filled using AFF. However, the V- and X-shaped THs could be fully filled using ACF. TH and microvias could be simultaneously filled in one plating bath using the AFF. A filling mechanism based on an adsorption/ consumption/diffusion mode was proposed to explain these plating results.
94 citations
01 Jan 2014
TL;DR: This paper presents a meta-modelling and simulation procedure that automates the very labor-intensive and therefore time-heavy and expensive process of copper electrodepositon and additive chemistry for on- chip interconnects.
Abstract: Preface (Kazuo Kondo) PART 1 Copper electrodepositon and additive chemistry Chapter 1 - Copper electrodeposition (Masayuki Yokoi) Chapter 2 - Suppression effect and Additive Chemistry (Masayuki Yokoi) Chapter 3- Acceleration effect (Dale P. Barkey) Chapter 4- Modeling and Simulation ( Yutaka Kaneko) PART 2 Copper on chip metallization Chapter 5- Frontiers of Cu Electrodeposition and Electroless Plating for On-Chip Interconnects (James R. Rohan) Chapter 6- Microstructure of Evolution of Copper in Nano-scale Interconnect Features (James Kelly, Christopher Parks, James Demarest, and Christopher Penny) Chapter 7- Direct Copper Plating (Aleksandar Radisic and Philippe M. Vereecken) Part 3 - Through Silicon Via and Other Methods Chapter 8- Through Silicon Via (Kazuo Kondo) Chapter 9- Build-up Printed Wiring board (Kiyoshi Takagi a and Toshkazu Okubo) Chapter 10- Copper Foil Smooth on Both Sides for Lithium Ion Battery (Akitoshi Suzuki and Jun Shinozaki) Chapter 11- Through hole plating (Wei-Ping Dow)
82 citations
References
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TL;DR: Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, theaverage number of blocks per module.
Abstract: Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, the average number of blocks per module. In the first region, P = KBr, where K is the average number of pins per block and 0.57 ≤ r ≤ 0.75. In the second region, that is, where the number of modules is small (i.e., 1-5), P is less than predicted by the above formula and is given by a more complex relationship. These conclusions resulted from controlled partitioning experiments performed using a computer program to partition four logic graphs varying in size from 500 to 13 000 circuits representing three different computers. The size of a block varied from one NOR circuit in one of the block graphs to a 30-circuit chip in one of the other block graphs.
725 citations
"Development of sequential build-up ..." refers background in this paper
...where G is the number of gates within an LSI, N is the I/O pin count and a, b are constants [ 3 ]....
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IBM1
TL;DR: The surface laminar circuit (SLC) as discussed by the authors is a component carrier technology which satisfies various requirements for packaging of small computers through its surface Laminar structure, which is similar to semiconductor wiring.
Abstract: Discusses the SLC (surface laminar circuit), a component carrier technology which satisfies various requirements for packaging of small computers through its surface laminar structure, which is similar to semiconductor wiring. By utilizing photo via holes instead of plated through holes for signal line connection, SLC has a high wiring density which allows it to carry bare chips directly attached on the SLC by flip chip attach. This packaging technology has an extended reliability compared with conventional flip chip bonding and a wide range of application in small computers. >
97 citations
9 citations
TL;DR: In this paper, a review of printed wiring boards (PWBs) for use in surface mounting technology (SMT) in Japan is presented, with particular emphasis on the high-density multilayer PWBs, which are important for SMT.
Abstract: Recent developments in printed wiring boards (PWBs) for use in surface mounting technology (SMT) in Japan are reviewed. Particular emphasis is placed on the high-density multilayer PWBs, which are important for SMT. Requirement for PWBs with respect to wiring density and housing capability, electrical properties, characteristics required at time of mounting, and reliability are discussed. Design, structure, and substrate materials are examined. The manufacture process is described. Quality assurance is addressed. Future prospects for PWBs are considered. >
7 citations