Device physics and design of T-gate Schottky barrier tunnel FET with adaptive operation mechanism
TL;DR: In this paper, a T-shaped gate Schottky barrier tunnel FET (TSB-TFET) is discussed in detail and experimentally demonstrated with compatible bulk Si CMOS technology, which can alleviate the major issues in traditional silicon TFET through adaptive operation mechanism, with higher ON-current from the dominant Schotty current, appreciably reduced off-leakage current from self-depletion effect, and steeper subthreshold slope (SS) from dominant band-to-band tunneling with enhanced source surface electric field through T-gate configuration
Abstract: A T-shaped gate Schottky barrier tunnel FET (TSB-TFET) is discussed in detail and experimentally demonstrated with compatible bulk Si CMOS technology. The device can alleviate the major issues in traditional silicon TFET through adaptive operation mechanism, with higher ON-current from the dominant Schottky current, appreciably reduced off-leakage current from self-depletion effect, and steeper subthreshold slope (SS) from dominant band-to-band tunneling with enhanced source surface electric field through T-gate configuration. Without area penalty, the fabricated silicon-based device can achieve steeper SS over more than 4 decades of current and thus lower average SS, as well as higher ION/IOFF ratio of 106 compared with traditional TFET. The parameters for device design and analog circuit applications are studied as well. Simulation results show that TSB-TFET can achieve excellent on-off current trade-off by lowering the Schottky barrier height, and also demonstrate lower gate-to-drain capacitance and better analog parameters performance than traditional TFET.
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TL;DR: In this paper, the impact of high-k/low-k gate dielectric materials on the ON-current and OFF-current of the heterogate junctionless tunnel field effect transistor (FET) was investigated.
Abstract: Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current ($$I_{\mathrm{ON}}$$ION) and OFF-current ($$I_{\mathrm{OFF}}$$IOFF) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high $$I_{\mathrm{ON}}$$ION and low $$I_{\mathrm{OFF}}$$IOFF current. The impact of work function variations and doping on device performance is also comprehensively investigated.
47 citations
TL;DR: The proposed DM-DCTGTFET biosensor is a highly promising structure due to dual sensing capabilities for biomolecules which are significantly higher than the recently reported TFET based biosensors.
Abstract: A dielectric modulated dual channel trench gate tunnel FET (DM-DCTGTFET) based biosensor is proposed for label-free detection of biomolecules. The gate of DM-DCTGTFET is placed vertically in a trench for creating two channels on both sides of the gate. The parallel conduction of two channels enhances the current of the DM-DCTGTFET. Further, in the proposed structure, two cavities are carved in the gate-oxide on either side of gate for biomolecules immobilization. The sensitivity performance of DM-DCTGTFET is analyzed using 2D simulations in the TCAD tool (ATLAS). The proposed structure exhibits high current sensitivity (~1012) as well as exorbitant voltage sensitivity ( $5.2 {V}$ ) which are significantly higher than the recently reported TFET based biosensors. Therefore, the DM-DCTGTFET biosensor is a highly promising structure due to dual sensing capabilities for biomolecules.
47 citations
30 Apr 2020
TL;DR: In this article, a vertical p-type tunnel FET (TFET) co-integrated on the same flake with a 2D MOSFET in a WSe2/SnSe2 material system platform is reported.
Abstract: Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.
43 citations
TL;DR: In this paper, an analytical model on the current-voltage characteristics of cylindrical surrounding gate p-n-i-n tunnel field effect transistor (TFET) is developed.
Abstract: An analytical model on the current–voltage characteristics of cylindrical surrounding gate p-n-i-n tunnel field-effect transistor (TFET) is developed. The model was derived by dividing the source, drain and channel regions into several portions so that some simple approximations for the surface potential across the tunneling junction and the channel can be achieved. Tunneling current is then calculated analytically by integrating the generation rate using the developed surface potential expressions over different regions. The results are verified with TCAD simulations. Good agreements in potential profile, transfer and output characteristics under different biasing conditions and with different device parameters are obtained. The applicability of this model for short-channel device is also discussed.
26 citations
Dissertation•
27 Nov 2018TL;DR: In this paper, a study of FDSOI tunnel FETs from planar to trigate/nanowire structures is presented, where functional low-temperature TFETs are fabricated with low-thermal budget (630°C) process flow, specifically designed for top tier devices in 3D sequential integration.
Abstract: This thesis presents a study of FDSOI Tunnel FETs (TFETs) from planar to trigate/nanowire structures. For the first time we report functional “Low-Temperature” (LT) TFETs fabricated with low-thermal budget (630°C) process flow, specifically designed for top tier devices in 3D sequential integration. “Dual IDVDS” method confirms that these devices are real TFETs and not Schottky FETs. Electrical characterization shows that LT TFETs performance is comparable with “High-Temperature” (HT) TFETs (1050°C). However, LT TFETs exhibit ON-current enhancement, OFF-current degradation and VTH shift with respect to HT TFETs that cannot be explained via BTBT mechanism. Charge pumping measurements reveal a higher defect density at the top silicon/oxide interface for geometries with narrow widths in LT than HT TFETs. In addition, low-frequency noise analyses shed some light on the nature of these defects. In LT TFETs, we determined a non-uniform distribution of defects at the top surface and also at the tunneling junction that causes trap-assisted tunneling (TAT). TAT is responsible of the current generation that degrades the subthreshold swing. This indicates the tight requirements for quality epitaxy growth and junction optimization in TFETs. Finally, we proposed novel TFET architectures. TCAD study shows that the extension of the source into the body region provides vertical BTBT and a larger tunneling surface. Ultra-thin heavily doped boron layers could allow the possibility to obtain simultaneously a good ON-current and sub-thermal subthreshold slope in TFETs.
4 citations
Cites background from "Device physics and design of T-gate..."
...In an attempt to solve the problem of the low on-current a T-gate Schottky barrier Tunnel FET (TSB-TFET) was proposed [70]....
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...(b) Schematic representation of a TSB-TFET and top view with the geometry description [70]....
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References
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
15 Jun 2010
TL;DR: In this paper, a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation was reported.
Abstract: We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation It produces steep subthreshold swing (SS) of 46mV/dec and high I ON /I OFF ratio (∼108) and the experiment was successfully repeated after two months Its superior operation is explained through simulation For the first time convincing statistical evidence of sub-60mV/dec SS is presented More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data
199 citations
05 Dec 2005
TL;DR: Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05/10 as discussed by the authors.
Abstract: Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05-10
194 citations
TL;DR: This paper provides an estimate of the effective output capacitance and drive current and a three-point model is proposed to extract the effective drive current from the real-time switching current trajectory in a TFET inverter.
Abstract: Through mixed-mode device and circuit simulation, this paper provides an estimate of the effective output capacitance (C EFF) and drive current (I EFF) for delay (tauf = 0.69 R sw C EFF, where R sw = V DD/2 I EFF) estimation of unloaded tunnel field-effect transistor (TFET) inverters. It is shown that unlike MOSFET inverters, where C EFF is approximately equal to the gate capacitance (C gg) , in TFET inverters, the output capacitance can be as high as 2.6 times the gate capacitance. A three-point model is proposed to extract the effective drive current from the real-time switching current trajectory in a TFET inverter.
188 citations
01 Dec 2009
TL;DR: In this article, tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high I on /I off ratio (≫104).
Abstract: Vertical In 0.53 Ga 0.47 As tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high I on /I off ratio (≫104). At V DS = 0.75V, a record on-current of 20µA/µm is achieved due to higher tunneling rate in narrow tunnel gap In 0.53 Ga 0.47 As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling. The measured data are in excellent agreement with two-dimensional numerical simulation at all drain biases. A novel 6T TFET SRAM cell using virtual ground assist is demonstrated despite the asymmetric source/drain configuration of TFETs.
147 citations