Device scaling limits of Si MOSFETs and their application dependencies

doi:10.1109/5.915374

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Device scaling limits of Si MOSFETs and their application dependencies

Journal Article•DOI•

Device scaling limits of Si MOSFETs and their application dependencies

David J. Frank¹, R.H. Dennard¹, E. J. Nowak¹, Paul M. Solomon¹, Yuan Taur¹, Hon-Sum Philip Wong¹ - Show less +2 more•Institutions (1)

IBM¹

01 Mar 2001-Vol. 89, Iss: 3, pp 259-288

TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Book•

Fundamentals of Modern VLSI Devices

[...]

Yuan Taur¹, Tak H. Ning¹•Institutions (1)

IBM¹

01 Jan 2016

TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.

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Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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2,680 citations

Journal Article•DOI•

Electron and ambipolar transport in organic field-effect transistors.

[...]

Jana Zaumseil, Henning Sirringhaus

23 Mar 2007-Chemical Reviews

2,020 citations

Journal Article•DOI•

Nanoelectronics from the bottom up

[...]

Wei Lu¹, Charles M. Lieber²•Institutions (2)

University of Michigan¹, Harvard University²

01 Nov 2007-Nature Materials

TL;DR: This review presents a brief summary of bottom-up and hybrid bottom- up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers.

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Abstract: Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

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1,537 citations

Cites methods from "Device scaling limits of Si MOSFETs..."

...But as device features are pushed towards the deep sub-100-nm regime, the conventional scaling methods of the semiconductor industry face increasing technological and fundamental challenge...
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Book•

FinFETs and Other Multi-Gate Transistors

[...]

Jean-Pierre Colinge

17 Oct 2007

TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.

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Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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843 citations

Additional excerpts

...Extended Abstracts of the International Conference on Solid State Devices and Materials (SSDM), 68 (2002) 59 B.S. Doyle, S. Datta, M. Doczy, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau: High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters 24-4, 263 (2003) 60 J.T. Park, J.P. Colinge, C. H. Diaz: Pi-gate SOI MOSFET. IEEE Electron Device Letters 22, 405 (2001) 61 J.T. Park and J.P. Colinge: Multiple-gate SOI MOSFETs: device design guidelines. IEEE Transactions on Electron Devices 49-12, 2222 (2002) 62 F.L. Yang, H.Y. Chen, F.C. Cheng, C.C. Huang, C.Y. Chang, H.K. Chiu, C.C. Lee, C.C. Chen H.T. Huang, C.J. Chen, H.J. Tao, Y.C. Yeo, M.S. Liang, C. Hu: 25 nm CMOS Omega FETs. Technical Digest of IEDM, 255 (2002) 63 Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Cheng Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao, Yee-Chia Yeo, Yiming Li, Jam-Wem Lee, Pu Chen, Mong-Song Liang, Chenming Hu: 5nm-gate nanowire FinFET. Symposium on VLSI Technology, 196 (2004) 64 R. Ritzenthaler, C. Dupré, X. Mescot, O. Faynot, T. Ernst, J.C. Barbé, C. Jahan, L. Brévard, F. Andrieu, S. Deleonibus, S. Cristoloveanu: Mobility behavior in narrow Ω-gate FET devices. Proceedings IEEE International SOI Conference, 77 (2006) 65 Z....
[...]
...Extended Abstracts of the International Conference on Solid State Devices and Materials (SSDM), 68 (2002) 59 B.S. Doyle, S. Datta, M. Doczy, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau: High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters 24-4, 263 (2003) 60 J.T. Park, J.P. Colinge, C. H. Diaz: Pi-gate SOI MOSFET. IEEE Electron Device Letters 22, 405 (2001) 61 J.T. Park and J.P. Colinge: Multiple-gate SOI MOSFETs: device design guidelines. IEEE Transactions on Electron Devices 49-12, 2222 (2002) 62 F.L. Yang, H.Y. Chen, F.C. Cheng, C.C. Huang, C.Y. Chang, H.K. Chiu, C.C. Lee, C.C. Chen H.T. Huang, C.J. Chen, H.J. Tao, Y.C. Yeo, M.S. Liang, C. Hu: 25 nm CMOS Omega FETs. Technical Digest of IEDM, 255 (2002) 63 Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Cheng Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao, Yee-Chia Yeo, Yiming Li, Jam-Wem Lee, Pu Chen, Mong-Song Liang, Chenming Hu: 5nm-gate nanowire FinFET....
[...]
...Extended Abstracts of the International Conference on Solid State Devices and Materials (SSDM), 68 (2002) 59 B.S. Doyle, S. Datta, M. Doczy, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau: High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters 24-4, 263 (2003) 60 J....
[...]
...Extended Abstracts of the International Conference on Solid State Devices and Materials (SSDM), 68 (2002) 59 B.S. Doyle, S. Datta, M. Doczy, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau: High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters 24-4, 263 (2003) 60 J.T. Park, J.P. Colinge, C. H. Diaz: Pi-gate SOI MOSFET. IEEE Electron Device Letters 22, 405 (2001) 61 J.T. Park and J.P. Colinge: Multiple-gate SOI MOSFETs: device design guidelines. IEEE Transactions on Electron Devices 49-12, 2222 (2002) 62 F....
[...]
...Extended Abstracts of the International Conference on Solid State Devices and Materials (SSDM), 68 (2002) 59 B.S. Doyle, S. Datta, M. Doczy, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau: High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters 24-4, 263 (2003) 60 J.T. Park, J.P. Colinge, C. H. Diaz: Pi-gate SOI MOSFET. IEEE Electron Device Letters 22, 405 (2001) 61 J.T. Park and J.P. Colinge: Multiple-gate SOI MOSFETs: device design guidelines. IEEE Transactions on Electron Devices 49-12, 2222 (2002) 62 F.L. Yang, H.Y. Chen, F.C. Cheng, C.C. Huang, C.Y. Chang, H.K. Chiu, C.C. Lee, C.C. Chen H.T. Huang, C.J. Chen, H.J. Tao, Y.C. Yeo, M.S. Liang, C. Hu: 25 nm CMOS Omega FETs. Technical Digest of IEDM, 255 (2002) 63 Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Cheng Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao, Yee-Chia Yeo, Yiming Li, Jam-Wem Lee, Pu Chen, Mong-Song Liang, Chenming Hu: 5nm-gate nanowire FinFET. Symposium on VLSI Technology, 196 (2004) 64 R....
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Journal Article•DOI•

A single-atom transistor

[...]

Martin Fuechsle¹, Jill A. Miwa¹, Suddhasatta Mahapatra¹, Hoon Ryu², Sunhee Lee³, Oliver Warschkow⁴, Lloyd C. L. Hollenberg⁵, Gerhard Klimeck³, Michelle Y. Simmons¹ - Show less +5 more•Institutions (5)

University of New South Wales¹, Korea Institute of Science and Technology Information², Purdue University³, University of Sydney⁴, University of Melbourne⁵

01 Apr 2012-Nature Nanotechnology

TL;DR: This work presents atomic-scale images and electronic characteristics of these atomically precise devices and the impact of strong vertical and lateral confinement on electron transport and discusses the opportunities ahead for atomic- scale quantum computing architectures.

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Abstract: The ability to control matter at the atomic scale and build devices with atomic precision is central to nanotechnology. The scanning tunnelling microscope can manipulate individual atoms and molecules on surfaces, but the manipulation of silicon to make atomic-scale logic circuits has been hampered by the covalent nature of its bonds. Resist-based strategies have allowed the formation of atomic-scale structures on silicon surfaces, but the fabrication of working devices-such as transistors with extremely short gate lengths, spin-based quantum computers and solitary dopant optoelectronic devices-requires the ability to position individual atoms in a silicon crystal with atomic precision. Here, we use a combination of scanning tunnelling microscopy and hydrogen-resist lithography to demonstrate a single-atom transistor in which an individual phosphorus dopant atom has been deterministically placed within an epitaxial silicon device architecture with a spatial accuracy of one lattice site. The transistor operates at liquid helium temperatures, and millikelvin electron transport measurements confirm the presence of discrete quantum levels in the energy spectrum of the phosphorus atom. We find a charging energy that is close to the bulk value, previously only observed by optical spectroscopy.

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821 citations

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References

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Journal Article•DOI•

Introduction to Solid State Physics

[...]

Charles Kittel, J. F. Masi

01 Aug 1954-Physics Today

23,110 citations

Book•

Introduction to solid state physics

[...]

Charles Kittel

01 Jan 1953

TL;DR: In this paper, the Hartree-Fock Approximation of many-body techniques and the Electron Gas Polarons and Electron-phonon Interaction are discussed.

...read moreread less

Abstract: Mathematical Introduction Acoustic Phonons Plasmons, Optical Phonons, and Polarization Waves Magnons Fermion Fields and the Hartree-Fock Approximation Many-body Techniques and the Electron Gas Polarons and the Electron-phonon Interaction Superconductivity Bloch Functions - General Properties Brillouin Zones and Crystal Symmetry Dynamics of Electrons in a Magnetic Field: de Haas-van Alphen Effect and Cyclotron Resonance Magnetoresistance Calculation of Energy Bands and Fermi Surfaces Semiconductor Crystals I: Energy Bands, Cyclotron Resonance, and Impurity States Semiconductor Crystals II: Optical Absorption and Excitons Electrodynamics of Metals Acoustic Attenuation in Metals Theory of Alloys Correlation Functions and Neutron Diffraction by Crystals Recoilless Emission Green's Functions - Application to Solid State Physics Appendix: Perturbation Theory and the Electron Gas Index.

...read moreread less

21,954 citations

Journal Article•DOI•

Introduction to Solid State Physics

[...]

A R Plummer

01 Jul 1967-Physics Bulletin

TL;DR: Kind's new edition is to be welcomed as mentioned in this paper, with a revised format and attractive illustrations, and with the inclusion of much new material this book has become one of the best sources for undergraduate teaching, likely to give the student a wish to dig deeper into the solid state.

...read moreread less

Abstract: 3rd edition, complete modern revision C. Kittel London: John Wiley. 1966. Pp. 648. Price £4 14s. Kind's new edition is to be welcomed. There is a revised format and attractive illustrations, and with the inclusion of much new material this book has become one of the best sources for undergraduate teaching. It is above all an interesting book, likely to give the student a wish to dig deeper into the solid state.

...read moreread less

5,704 citations

"Device scaling limits of Si MOSFETs..." refers background in this paper

...can be estimated from the particle-in-a-box approximation for the lowest subband [11], [12], [53], giving ....
[...]

Journal Article•DOI•

High-performance heat sinking for VLSI

[...]

David B. Tuckerman¹, Roger Fabian W. Pease¹•Institutions (1)

Stanford University¹

01 May 1981-IEEE Electron Device Letters

TL;DR: In this paper, a water-cooled integral heat sink for silicon integrated circuits has been designed and tested at a power density of 790 W/cm2, with a maximum substrate temperature rise of 71°C above the input water temperature.

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Abstract: The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

...read moreread less

4,214 citations

"Device scaling limits of Si MOSFETs..." refers background in this paper

...It was demonstrated in 1981 that nearly 1 KW/cm could be removed from a Si wafer [80] by forcing liquid coolant through channels etched into the back of a Si...
[...]

Journal Article•DOI•

Design of ion-implanted MOSFET's with very small physical dimensions

[...]

R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, A. LeBlanc - Show less +1 more

01 Oct 1974-IEEE Journal of Solid-state Circuits

TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.

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Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

...read moreread less

3,008 citations