Dielectric Reliability Measurement Methods: A Review
20 Feb 1998-Microelectronics Reliability (Pergamon)-Vol. 38, Iss: 1, pp 37-72
TL;DR: A review of the most common dielectric reliability measurement methods can be found in this paper, where a broad number of different measurement techniques are described in detail for which the set up of the measurement and its stress parameters are clarified.
Abstract: Reliability of thin dielectric films such as silicon dioxide grown on single crystalline silicon is of great importance for integrated circuits of present and future technologies. For the characterization of the quality of dielectric films, it is essential to have measurement methods available which can give a measure of dielectric reliability in a relatively short time. Stress biases are usually highly accelerated and cause destructive dielectric breakdown. Testing for dielectric reliability has been performed for more than 30 years, and in that time many different stress methods have been established. This article reviews that most common dielectric reliability measurement methods and gives practical guidelines to the reliability engineer in the field of dielectric characterization. The examples and data shown here are mainly from MOS gate oxides. The aim of this review paper is to emphasize advantages and disadvantages of the various stress methods. Appropriate dielectric stress methods are pointed out for applications such as process development, process characterization, pocess control and screening (burn-in). A broad number of different measurement techniques are described in detail for which the set up of the measurement and its stress parameters are clarified. Suitable dielectric test structures and the determination of the correct voltage and thickness of the dielectric are discussed; they are essential to determine the electric field across the thin film. The identification of dielectric breakdown and the interpretation and significance of the measurement results are reviewed. A good understanding of the stress method and the various measured parameters is essential to draw correct conclusions for the lifetime of the dielectric at operating conditions. The commonly used, basic analysis techniques for the measurement results are illustrated. Finally, the influence of stress-induced leakage currents on the dielectric reliability characterization is discussed and other aspects relating to very thin oxides of future technologies are briefly described. The paper also includes a large bibliography of more than 250 references.
TL;DR: In this paper, the authors focus on the case of gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm.
Abstract: In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...
TL;DR: In this paper, the recent developments of (Ba,Sr)TiO 3 (BST) thin films for future Gbit era dynamic random access memory (DRAM) applications are reviewed.
Abstract: This paper reviews the recent developments of (Ba,Sr)TiO 3 (BST) thin films for future Gbit era dynamic random access memory (DRAM) applications. The trends of DRAM capacitors in the last decade are briefly described first. Then the technological aspects of BST films such as deposition techniques, post-annealing, physical, electrical and dielectric characteristics of the films, effects of electrode materials, dielectric relaxation and defect analysis and the reliability phenomena associated with the films are briefly reviewed with specific examples from recent literature. The basic mechanisms that control the bulk electrical conduction and the origin of leakage currents in BST films are also discussed. Finally, possible developments of gigabit era DRAM technology are summarized.
TL;DR: In this article, the authors review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics, and discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance.
Abstract: The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 mm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown, Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.
••30 Apr 2001
TL;DR: In this article, the physics and statistics of dielectric wearout and breakdown in ultra thin SiO/sub 2/--based CMOS gate dielectrics are discussed.
Abstract: This paper reviews the physics and statistics of dielectric wearout and breakdown in ultra thin SiO/sub 2/-based CMOS gate dielectrics. Electrons or holes tunneling through gate oxide generate defects until a critical density is reached and the oxide breaks down. Critical defect density is explained by defect percolation path formation across the oxide; <1% of these paths lead to destructive breakdown, and the microscopic nature of the defects is not known. Defect generation rate decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron induced hydrogen release, but tunnel current increases exponentially with decreasing oxide thickness, giving decreasing time-to-breakdown and a lower reliability margin as device dimensions are scaled. Estimating dielectric reliability requires extrapolation from measurement conditions to operational conditions. Due to the lower reliability margin, it is imperative to reduce extrapolation error. Long term stress experiments are used to measure ultra thin dielectric film wearout and breakdown as close as possible to operating conditions, and have revealed the voltage dependence of the defect generation rate and critical defect density, allowing better time-to-breakdown voltage dependence modeling. Such measurements are used to guide pre-manufacturing technology development. We discuss electrical conduction through a breakdown spot, and the effect of oxide breakdown on device and circuit performance. In some cases, oxide breakdown does not lead to immediate circuit failure, and a quantitative methodology to predict circuit reliability must be developed.
TL;DR: In this article, the main features of the extraction of electrons from cold metals by intense electric fields are well known, and an approximate theory of the effect was first developed by Schottky.
Abstract: 1. Introduction .—The main features of the phenomenon of the extraction of electrons from cold metals by intense electric fields are well known, and an approximate theory of the effect was first developed by Schottky. More recently the experimental data have been much improved, notably by Millikan and Eyring, and Millikan and Lauritsen. The theory has been considered afresh by O. W. Richardson and by Houston working with Sommerfeld. It seems to us, however, that there is still room for improvement in the theoretical exposition and its correlation with the experiments. Neither O. W. Richardson nor Houston really treat the theory in the simple straightforward way which is now possible in the new mechanics, using the revived electron theory of metals which we owe to Sommerfeld. Again, while Millikan and Lauritsen seem to have established quite definitely the laws of dependence of the emission on the field strength F, they speak of the implications of their result in a way which is hard to justify and might in certain circumstances prove to be definitely misleading. Millikan and Lauritsen show that a plot of log I, where I is the current, against 1/F yields a good straight line whenever the experimental conditions are sufficiently stable. At ordinary temperatures these currents are completely independent of the temperature. The formula for these current is I = C e ─a /F, (1) Which is, of course, indistinguishable from I = CF2 e ─a /F. (2) Millikan and his associates have also shown that as the higher temperatures, at which ordinary thermionic emission begins, are approached, the strong field emission does become sensitive to temperature and finally blends into the thermionic.
TL;DR: In this article, the relative effective mass in the forbidden energy gap was found to be about 0.4, which is lower by a factor of five to ten than the expected values, probably due to trapping effects.
Abstract: Electronic conduction in thermally grown SiO2 has been shown to be limited by Fowler‐Nordheim emission, i.e., tunneling of electrons from the vicinity of the electrode Fermi level through the forbidden energy gap into the conduction band of the oxide. Fowler‐Nordheim characteristics have been observed over more than five decades of current for emission from Si, Al, and Mg. If previously measured values of the barrier heights are used, the slopes of the Fowler‐Nordheim characteristics (log J/E2 vs 1/E) imply values of the relative effective mass in the forbidden band of about 0.4. These values take into account corrections for image‐force barrier lowering and for temperature effects. The absolute values of the currents are lower by a factor of five to ten than the theoretically expected values, probably due to trapping effects. The temperature dependence of the current was found to follow the theoretical curve from 80°–420°K. However, an inconsistent relative effective mass of about 0.95 had to be assumed....
TL;DR: In this article, two mechanisms triggered by electron heating in the oxide conduction band are discussed: trap creation and band gap ionization by carriers with energies exceeding 2 and 9 eV, respectively.
Abstract: Degradation of silicon dioxide films is shown to occur primarily near interfaces with contacting metals or semiconductors. This deterioration is shown to be accountable through two mechanisms triggered by electron heating in the oxide conduction band. These mechanisms are trap creation and band‐gap ionization by carriers with energies exceeding 2 and 9 eV with respect to the bottom of the oxide conduction band, respectively. The relationship of band‐gap ionization to defect production and subsequent degradation is emphasized. The dependence of the generated sites on electric field, oxide thickness, temperature, voltage polarity, and processing for each mechanism is discussed. A procedure for separating and studying these two generation modes is also discussed. A unified model from simple kinetic relationships is developed and compared to the experimental results. Destructive breakdown of the oxide is shown to be correlated with ‘‘effective’’ interface softening due to the total defect generation caused by both mechanisms.
TL;DR: In this paper, a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 /spl Aring/ and 130 /spl Ring/, is presented, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses.
Abstract: In this paper, we present a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 /spl Aring/ and 130 /spl Aring/, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. This model, based on hole injection from the anode, accurately predicts Q/sub BD/ and t/sub BD/ behavior including a fluence in excess of 10/sup 7/ C/cm/sup 2/ at an oxide voltage of 2.4 V for a 25 /spl Aring/ oxide. Moreover, this model is a refinement of and fully complementary with the well known 1/E model, while offering the ability to predict oxide reliability for low voltages. >