Digital Integrated Circuits
Citations
3,190 citations
Additional excerpts
...Inverters can be implemented with two ptype transistors in either an enhancementload or a depletion-load configuration (18)....
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978 citations
911 citations
Cites background from "Digital Integrated Circuits"
..., low-power synthesis and cell-based design—, also and particularly in the future [10]....
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...5 ( , [10]), and this ratio will decrease even further in deep-submicron technologies, where the carrier drift velocities in NMOS and PMOS transistors become almost equal due to velocity saturation [11]....
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754 citations
Cites methods from "Digital Integrated Circuits"
...When the application is executed in the mobile device, the computation energy can be minimized by optimally scheduling the CPU clock frequency of the mobile device via the Dynamic Voltage Scaling (DVS) [9]....
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...For the mobile execution, its total energy consumption can be minimized by optimally configuring the clock frequency of the chip via DVS [9]....
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495 citations
Cites methods from "Digital Integrated Circuits"
...If the number of devices switching per clock cycle is N, the clock frequency is f , the average load capacitance that a device has to drive is C, and the power supply voltage is VDD, then the power consumption PD of digital circuits is given by the simple formula (Rabaey, 1996), PD = Nf CVDD2....
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...If the number of devices switching per clock cycle is N, the clock frequency is f , the average load capacitance that a device has to drive is C, and the power supply voltage is VDD, then the power consumption PD of digital circuits is given by the simple formula (Rabaey, 1996),...
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