Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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NEC1
TL;DR: A fault diagnosis algorithm based on path tracing which dynamically extracts partial circuits and traces error propagation paths from failing primary outputs to a fault origin is proposed, and the improved technique localizes faults effectively in a reasonable time.
Abstract: We have proposed a fault diagnosis algorithm based on path tracing which dynamically extracts partial circuits and traces error propagation paths from failing primary outputs to a fault origin. Logic inference and the rating procedures are improved, so that various fault modes such as stuck-at, open and bridge faults can be diagnosed. We have shown that the improved technique localizes faults effectively in a reasonable time by applying it to several scan-based circuits: 20 K-gate benchmark circuits (ISCAS'89), and 100 K- and 2M-gate industrial circuits.
24Â citations
TL;DR: A dynamic algorithm for test sequence compaction and test application time (TAT) reduction in combinational and sequential circuits and a sliding anchor frame technique to specify the unspecified inputs in a test sequence is proposed.
Abstract: We present a dynamic algorithm for test sequence compaction and test application time (TAT) reduction in combinational and sequential circuits. Several dynamic test compaction algorithms for combinational circuits have been proposed. However, few dynamic methods have been reported in the literature for sequential circuits. Our algorithm is based on two key ideas: (1) at any point during the test generation process, we identify bottlenecks that prevent vector compaction and TAT reduction for test sequences generated thus far, and (2) future test sequences are generated with an aim to eliminate bottlenecks of earlier generated test sequences. If all bottlenecks of a test sequence are eliminated, the sequence is dropped from the test set. Our algorithm can also target TAT reduction under the recently proposed partial scan-in/scan-out model by identifying and eliminating scan bottlenecks. If only the scan bottlenecks of a test sequence are eliminated, the test sequence can be trimmed to reduce the scan-in/scan-out cycles required to apply the sequence. For sequential circuits, we propose a sliding anchor frame technique to specify the unspecified inputs in a test sequence. The anchor frame is the first frame processed by a sequential test generator that is based on an iterative array model of the circuit, and the vector corresponding to the anchor frame is called the anchor vector. Under the sliding anchor frame technique, every vector in the test sequence being extended is considered as an anchor vector. This has the same effect as allowing observation of fault effects at every vector in the sequence, leading to a higher quality of compaction. The final test set generated by our algorithm cannot be further compacted using many known static vector compaction or TAT reduction techniques. For example, reverse or any other order of fault simulation, along with any specification of unspecified values in test sequences, cannot further reduce the number of vectors or TAT. Experimental results on combinational and sequential benchmark circuits, and large production VLSI circuits are reported to demonstrate the effectiveness of our approach.
24Â citations
Cites methods from "Digital Systems Testing and Testabl..."
...Sequential test generators based on the iterative array model of the circuit process time-frames in several different ways [ 32 ]....
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Patent•
09 Feb 2010TL;DR: In this paper, a test cube is generated targeting one or more faults in the circuit design and then modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.
Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.
24Â citations
TL;DR: How the number of faults to be simulated in an analog circuit can be reduction by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks is described.
Abstract: Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.
24Â citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Techniques, such as concurrent fault simulation [ 2 ], exploit the fact that the differences in behavior between the faulty and fault-free circuits are often relatively small, and by avoiding redundant element evaluation, reduce the computational effort required to evaluate all the faulty circuit copies....
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...The testing methodology therefore becomes one of identifying the presence or otherwise of these structural faults [ 2 ,3]....
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...As the generation of the optimal set is unlikely to be feasible for anything other than the smallest circuits, algorithms such as the D-algorithm or PODEM are used to find a test pattern for one fault [ 2 ]....
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02 Oct 2005
TL;DR: An at-speed logic BIST architecture for testing multi-clock, multi-frequency designs and physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements.
Abstract: This paper presents an at-speed logic BIST architecture for testing multi-clock, multi-frequency designs. The scheme employed allows true at-speed test quality for circuits containing multiple clocks without any clock frequency manipulation. Physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements. Application results for two industrial designs are also reported.
24Â citations
Cites methods from "Digital Systems Testing and Testabl..."
...Logic Built-In Self-Test (BIST) [1-3] uses on-chip circuitry to generate test stimuli and analyze test responses, with little or no help from an ATE....
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