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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
Synchronous test generation model for asynchronous circuits
TL;DR: A new synchronous test model (STM) is proposed that captures the essential behavior of the circuit under test that generates test sets with high fault coverage and with absolutely no test invalidation.
Patent
Monolithic three-dimensional semiconductor device and structure
TL;DR: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistor as discussed by the authors.
Proceedings ArticleDOI
Computation of minimal counterexamples by using black box techniques and symbolic methods
TL;DR: The notion of 'uniform counterexamples' is introduced to provide an exact formalization of simplified countereXamples arguing only about components which were not masked out, based on symbolic methods using AIGs (And-Inverter-Graphs).
Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning
TL;DR: This paper starts by describing how Boolean Satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits, and shows how recursive learning techniques can be incorporated into Boolean Satisfiable algorithms.
Journal ArticleDOI
Verifying sequential equivalence using ATPG techniques
TL;DR: This paper addresses the problem of verifying the equivalence of two sequential circuits by identifying equivalent flip-flop pairs using an induction-based algorithm and generalizing the idea of exploring the structural similarity between circuits to perform verification in stages.