Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: A fault diagnosis technique which employs the Differential NonLinearity (DNL) test data for fault location and identification of the analog components in the converter and the concept and the detailed diagnosis algorithm are described.
Abstract: This paper addresses the problem of diagnosis of flash ADC's and proposes a fault diagnosis technique which employs the Differential NonLinearity (DNL) test data for fault location and identification of the analog components in the converter. In the flash ADC, a fault causes deviation of DNL data from the ideal one. Hence, DNL data can be considered as a functional signature of the ADC. This property is employed for fault diagnosis. DNL patterns are used for fault location, and DNL data are used to calculate the fault values. Both single fault cases and multiple fault cases are considered. The technique proposed here relies only on DNL test data and not on the test method, thus the diagnosis can be carried out using at-operating-speed test data. This paper describes the concept and the detailed diagnosis algorithm. Experiments have been carried out to verify the practicality of the technique. They are presented and discussed in detail. The limitations and practical implementation issues relating to the technique are also addressed.
22Â citations
07 Nov 1999
TL;DR: A timing-driven cell replication procedure is presented, its incorporation into a standard cell placement and routing tool is demonstrated, and its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques is examined.
Abstract: This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing driven layout synthesis. Therefore, this paper presents a timing driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques.
22Â citations
Patent•
19 Jun 1991TL;DR: In this article, a method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed, which is coupled to a binary constant generation and selection circuit which is also coupled to the system logic.
Abstract: A method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed. The embedded memory arrays are coupled to a binary constant generation and selection circuit which is also coupled to the system logic. During a test mode, the selection circuit sends a binary constant to the system logic in lieu of normal operational data output from the memory arrays. The system logic is tested while the binary constant is continuously applied.
22Â citations
TL;DR: In this paper, the authors present an automatic test generation (ATG)-based technique to efficiently generate tight lower bounds of the maximum power for large CMOS circuits under nonzero gate delays.
Abstract: With the high demand for reliability and performance, accurate estimation of maximum power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and to optimize the power and ground routing. Unfortunately, the problem of determining the input patterns to induce maximum current and, hence, the maximum power, is NP complete. Even for circuits with small number of primary inputs (PIs), it is CPU time intensive to conduct exhaustive search in the input vector space. In this paper we present an automatic test generation (ATG)-based technique to efficiently generate tight lower bounds of the maximum power for large CMOS circuits under nonzero gate delays. Power dissipation due to spurious transitions has been considered by incorporating static timing analysis into the estimation process. Experiments were performed on ISCAS and MCNC benchmarks. Results show that the ATG-based technique is superior to the traditional simulation-based technique in both speed and performance. On average, for sequential circuits having over 10000 gates (ISCAS-89 benchmarks), the ATG-based approach executes 261 times faster, and generates a lower bound which is 1.8 times better compared to simulation based approaches.
22Â citations
16 Apr 2007
TL;DR: A timing-based, power and layout-aware pattern generation technique that minimizes both global and localization switching activity and comprehends irregular power grid topologies for constraints on localized switching activity is proposed.
Abstract: With increasing use of low cost wire-bond packages for mobile devices, excessive dynamic IR-drop may cause tests to fail on the tester. Identifying and debugging such scan test failures is a very complex and effort-intensive process. A better solution is to generate correct-by-construction "power-safe" patterns. Moreover, with glitch power contributing to a significant component of dynamic power, pattern generation needs to be timing-aware to minimize glitching. In this paper, we propose a timing-based, power and layout-aware pattern generation technique that minimizes both global and localized switching activity. Techniques are also proposed for power-profiling and optimizing an initial pattern set to obtain a power-safe pattern set, with the addition of minimal patterns. The proposed technique also comprehends irregular power grid topologies for constraints on localized switching activity. Experiments on ISCAS benchmark circuits reveal the effectiveness of the proposed scheme
22Â citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...We use 8-valued logic, as explained in [17], for representing static and dynamic hazard....
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...The reader may refer to [17] for a description of the PODEM algorithm....
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...When there are several candidate gates in the D-frontier [17], the gates are evaluated on their timing window size and paObjective() selects the candidate gate having the least timing window size....
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...When there are several candidate gates in the D-frontier [17], the gates are evaluated on their timing window size and paObjective() selects the candidate gate having the least timing window size....
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