Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Patent•
15 Jun 2007TL;DR: In this paper, a full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit, which includes a shadow latch, a multiplexer, and a slave latch.
Abstract: A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.
22Â citations
01 Jul 1993
TL;DR: Simulation results demonstrate that the proposed timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing (using reasonable computing time).
Abstract: Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. Both more functions and higher speed are required in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate resizing. To control hardware overhead, a minimum (or as small as possible) number of gates are selected for resizing with the aid of a powerful benefit function. To guarantee the performance of timing optimization, a modified version of PODEM ensures that each resized gate is located on at least one critical path. Thus, resizing a gate definitely reduces circuit delay. Simulation results demonstrate that our timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing (using reasonable computing time).
22Â citations
Cites background or result from "Digital Systems Testing and Testabl..."
...In other words, this operation is similar to the fault simulation operation in test generation for stuck-at faults [35]....
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...The complete process stops when either a test vector is found or when the fault is determined to be untestable [1], [35], [36]....
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08 Nov 1992
TL;DR: An algorithm of complexity O(kN/sup 2/) is presented for configuring the chains such that the overall test application time is minimized and test time reductions as large as 40% over equal length chain configurations are demonstrated.
Abstract: To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper we consider the problem of optimally constructing multiple scan chains so as to minimize ovemll test time. Rather than follow the tmditional practice of using equal length chains, we allow the chains to be of different lengths, and show that this can lead to lower test times. The main idea in our approach is to assign those scan elements that are more frequently accessed to shorter scan chains. Given a design with N scan elements, and given that k scan chains are to be used for a pl in tests, we present an algorithm of complezity O(kN ) for configuring the chains such that the overall test application time is minimized. By analyzing a range of circuit topologies, we demonstrate test time reductions as large as 40% over equal length chain conjigurations. cyg
22Â citations
TL;DR: Experimental results indicate the high effectiveness of the proposed error rate estimation method, and the degree to which yield can be enhanced.
Abstract: Error-tolerance is an innovative technique to address the problem of low yields in nanometer very large scale integrated (VLSI) circuitry, which is the backbone of the system-on-a-chip (SOC) revolution. The basic principle of error-tolerance is that some chips may occasionally produce erroneous outputs, but still provide acceptable performance when used in certain systems. Using these chips in such systems results in an increase in effective yield. In this paper, a fault-oriented test methodology is presented for classifying whether or not a chip is acceptable based on error rate estimation. A sampling method is proposed to estimate error rate associated with each possible fault in the target circuit. According to this information, an approach is developed to identify a list of faults that are acceptable with respect to a specified upper bound on expected error rates of acceptable chips. Furthermore, a test pattern selection method, and an output masking technique are presented to identify tests which detect all of the unacceptable faults, and as few acceptable faults as possible, so as to maximize the effective yield. Experimental results indicate the high effectiveness of the proposed error rate estimation method, and the degree to which yield can be enhanced.
22Â citations
01 Apr 2001
TL;DR: Two algorithms based on automatic test pattern generation (ATPG) can finish the largest benchmark circuit within ten seconds, and achieve up to 87% larger current when compared to an existing ATPG-based estimation algorithm that is able to obtain maximum current estimation 6% less than the theoretical maximum current.
Abstract: As semiconductor technology scales down, the leakage power will soon become comparable to the dynamic power. To reduce both dynamic and leakage power, power gating in addition to clock gating should be used because clock gating saves only dynamic power. The knowledge of maximum current is needed to design high-performance and reliable circuits using power gating. However, all existing techniques for maximum current estimation are not applicable to power gating. In this paper, we study the maximum current estimation problem considering power gating. We develop two algorithms based on automatic test pattern generation (ATPG), and apply them to ISCAS'85 benchmarks. Experiments show that our new estimation algorithms can finish the largest benchmark circuit within ten seconds, and achieve up to 87% larger current when compared to an existing ATPG-based estimation algorithm that is able to obtain maximum current estimation 6% less than the theoretical maximum current without considering power gating. This implies that power gating may lead to a larger maximum current when compared to the normal maximum switching current, and open a new avenue for maximum current estimation as well as circuit reliability research.
22Â citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Backtrace(obj) is also a recursive subroutine, and it is di erent from that in the original PODEM algorithm [16] [17] in terms of how to select the path to backtrace....
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...We use the PODEM algorithm [16] [17] to generate our one input vector because PODEM is much more e cient and ts our problem formulation very well....
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...These two fundamental steps can be converted into a series of line-justi cation problems[17]....
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