Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Patent•
16 Nov 2012
TL;DR: In this paper, a method to form a monolithic 3D device including processing a first layer including first mono-crystal transistors, transferring a second mono-cstal layer on top of the first layer, and repairing the damage caused by the ion-cut by using optical annealing was presented.
Abstract: A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.
20 citations
01 Oct 2007
TL;DR: This paper proposes a design-for-test (DFT) method to make an arbitrary reversible logic circuit composed of n-bit Toffoli gates fully testable for single intra-level bridging faults and single stuck-at faults.
Abstract: Toffoli gate is a universal reversible logic gate by which any classical or quantum circuit can be synthesized In this paper, we propose a design-for-test (DFT) method to make an arbitrary reversible logic circuit composed of n-bit Toffoli gates fully testable for single intra-level bridging faults and single stuck-at faults We have considered testing of circuits composed of n-bit Toffoli gates The proposed method requires exactly ([log2N] +3) test vectors, for 'N' input wires, which is independent of the number of gates in the circuit We also give a universal test set for detecting these faults
20 citations
Cites background from "Digital Systems Testing and Testabl..."
...Lemma 1: A single bridging fault between any two lines at the same level in a reversible logic circuit can be detected by a test vector iff the two faulty lines receive opposite logic values (‘01’ or ‘10’) [ 16 ]....
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...A stuck-at fault fixes the logic value of any wire in the circuit to either 0 (stuck-at 0) or 1 (stuck-at 1). A stuck-at fault at any wire can be detected by assigning opposite logic values from the fault value [ 16 ]....
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01 Jan 1999
TL;DR: This thesis presents one approach to hardware/software interface synthesis that ranges from the specification to the implementation and validation of hardware/ software interface protocols, based on standard simulation methods and facilitates simulation of the interfaces at several steps during development.
Abstract: Design based on intellectual property (IP) is emerging to close the gap between steadily increasing capacity, in terms of transistors on integrated devices, and design productivity, in terms of the number of transistors designed in a given period. However, the integration of several IP blocks into a single system on one chip makes the specification and implementation of interfaces (for example, bus interfaces and device drivers) a dominant design problem for embedded systems. There is therefore a need for effective ways of modelling, refining, and implementing communication within embedded systems. This thesis presents one approach to hardware/software interface synthesis that ranges from the specification to the implementation and validation of hardware/software interface protocols. The information required for hardware/software interface synthesis is separated into three parts: the protocol specification, information related to the operating system, and information related to the processor. From these inputs a synthesis tool generates (a) device driver functions, (b) a combination of device driver functions and a DMA controller, or (c) simulation models, depending on what the designer decides. The clean separation of information facilitates (1) efficient design space exploration with combinations of different processors, operating systems and protocols, and (2) efficient maintenance of a large number of different versions and variants of hardware/software interfaces. The three-phase validation approach is based on standard simulation methods and facilitates simulation of the interfaces at several steps during development. We keep all the simulation models consistent with both the specification and the implementation by generating the models using the same technique that is used for synthesis. Validation in several phases is justified (1) by the faster simulation of early phases (up to four times faster than late phases), and (2) by allowing both hardware designers and software developers to work in their familiar tool environments as long as possible. Protocols are specified as a grammar, which is fully independent of architecture and implementation. After the initial selection of implementation alternatives, the methods presented are fully automated. Using real-life examples we demonstrate the effectiveness of the simulation models and show that the quality of the generated code is close to handwritten quality in terms of performance, area and code size.
20 citations
23 Sep 1994
TL;DR: This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are hazard free.
Abstract: This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are hazard free. The algorithm uses Binary Decision Diagrams (BDDs) for the computation and representation of the test sets. It has been implemented as the program BiTeS. The implementation is very simple, since only BDD operations must be carried out. BiTeS computes the complete set of patterns that lead to a test instead of a single test. Thus, methods for test set compaction can easily be applied. Experimental results are presented to demonstrate the e ciency of BiTeS.
20 citations
Cites background from "Digital Systems Testing and Testabl..."
...Every circuit has to be tested to check its correct behavior [1, 27]....
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03 Jan 2001
TL;DR: Experimental results on benchmark circuits are used to demonstrate rapid and accurate locating of multiple errors and the effectiveness of the region based model for gate connection and gate substitution errors.
Abstract: Algorithms to locate multiple design errors using region-based model are studied for both combinational and sequential circuits. The model takes locality aspect of errors and is based on a 3-value, non-enumerative analysis technique. Studies show the effectiveness of the region based model for gate connection and gate substitution errors. For sequential circuits, we try to locate the time frame at which the error was first excited, by re-simulating as few vectors as possible preceding the erroneous vector in a fully initialized circuit to carry out the diagnosis. Experimental results on benchmark circuits are used to demonstrate rapid and accurate locating of multiple errors.
20 citations