Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Proceedings Article•
01 Jan 2004
TL;DR: The results show that global unobservability constraints lead to small additional speedup if local unobservable is exploited, but make the SAT-time less dependent on values of parameters in the translation.
Abstract: The paper studies the use of global unobservability constraints in a CNF translation of Boolean formulas, where the unobservability of logic blocks is encoded with CNF unobservability variables and the logic output values of the blocks with CNF logic variables. Each block’s unobservability variable is restricted by local unobservability constraints, expressing conditions that the output value of the block will not propagate to the primary output, given values of inputs to nearby gates on the path to the primary output. Global unobservability constraints add conditions that a block is unobservable if all paths to the primary output pass through logic blocks that are unobservable. By introducing a cut of unobservability check-points at the inputs of the top gate in a Boolean formula, we can impose global unobservability constraints for every logic block. The results show that global unobservability constraints lead to small additional speedup if local unobservability is exploited, but make the SAT-time less dependent on values of parameters in the translation.
18 citations
Cites background from "Digital Systems Testing and Testabl..."
...Conventional translation to CNF [19] captures only local structural information for logic gates, and so does not exploit the concept of unobservability [2][18] (related to the concept of dominators in testing [1])—that the output values of subcircuits may be unobservable at the primary output, i....
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Patent•
02 May 2011
TL;DR: In this paper, a method for the design and manufacturing of a 3D semiconductor device including a first circuit stratum and a second circuit strata is presented. But the method is not suitable for 3D applications.
Abstract: A method for the design and manufacturing of a 3D semiconductor device including a first circuit stratum and a second circuit stratum, the method including: applying a synthesis tool with at least first and second technology libraries; and performing a synthesis that utilizes the at least first and second technology libraries, where the first and second technology libraries correspond to two different processes, where the first technology library targets the first circuit stratum and the second technology library targets the second circuit stratum, and where the performing a synthesis results in a netlist, the netlist includes first cells of the first technology library and second cells of the second technology library.
18 citations
30 Apr 2006
TL;DR: Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults.
Abstract: A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9 % to 44% average reduction in the fault simulation time for these circuits.
18 citations
11 Nov 1991
TL;DR: The authors present a test generation procedure for gate-level circuits which is based on multiple observation time units and multiple fault-free sequences, and they show that test sequences can be found by this procedure in cases where conventional test generators fail to find tests due to their failure to initialize the circuit.
Abstract: The authors consider the problem of test generation for synchronous sequential circuits for the case where no hardware reset is available, and show that initialization is not a necessary requirement for a practical test generator. They present a test generation procedure for gate-level circuits which is based on multiple observation time units and multiple fault-free sequences, and they show that test sequences can be found by this procedure in cases where conventional test generators fail to find tests due to their failure to initialize the circuit. Experimental results for ISCAS-89 benchmark circuits are presented to support the claim that fault coverage can be significantly increased, while requiring small numbers of observation times and small numbers of fault-free responses. >
18 citations
01 Jan 2002
TL;DR: A novel hybrid built-in self-test architecture is proposed, which makes use of both pseudorandom and deterministic test patterns, and is appropriate for modern system-on-chip designs and is suitable for testability designs.
Abstract: The technological development is enabling production of increasingly complex electronic systems. All those systems must be verified and tested to guarantee correct behavior. As the complexity grows, testing is becoming one of the most significant factors that contribute to the final product cost. The established low-level methods for hardware testing are not any more sufficient and more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. This thesis reports on one such work that deals in particular with high-level test generation and design for testability techniques. The contribution of this thesis is twofold. First, we investigate the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation architecture. We have developed for this purpose a novel hierarchical test generation algorithm and demonstrated the usefulness of the generated tests not only for manufacturing test but also for testability analysis. The second part of the thesis concentrates on design for testability. As testing of modern complex electronic systems is a very expensive procedure, special structures for simplifying this process can be inserted into the system during the design phase. We have proposed for this purpose a novel hybrid built-in self-test architecture, which makes use of both pseudorandom and deterministic test patterns, and is appropriate for modern system-on-chip designs. We have also developed methods for optimizing hybrid built-in self-test solutions and demonstrated the feasibility and efficiency of the proposed technique.
18 citations