Digital Systems Testing and Testable Design

Book•

Digital Systems Testing and Testable Design

Miron Abramovici, M.A. Breuer, Arthur D. Friedman

01 Jan 1990-

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.

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Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.

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Proceedings Article•DOI•

Accelerating Diagnosis via Dominance Relations between Sets of Faults

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R. Adapa¹, Spyros Tragoudas¹, Maria K. Michael²•Institutions (2)

Southern Illinois University Carbondale¹, University of Cyprus²

06 May 2007

TL;DR: Experimental results show that the proposed collapsing methods can reduce the diagnostic simulation time on an average of 31% when compared to the existing techniques.

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Abstract: A new way of fault collapsing for effect-cause diagnosis is presented. In contrast to existing dominance-based methods which operate on a pair of faults, the proposed method operates on pairs of sets of faults. The impact of the proposed method is evaluated with respect to effect-cause diagnosis. Experimental results show that the proposed collapsing methods can reduce the diagnostic simulation time on an average of 31% when compared to the existing techniques

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18 citations

Cites background from "Digital Systems Testing and Testabl..."

...The two classes of fault collapsing for stuck at faults are equivalence fault collapsing and dominance fault collapsing [1]....
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...Cause-effect diagnosis requires a large amount of memory to store failing responses and is not suitable for diagnosing large designs [1]....
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...These techniques backtrack from each failing primary output to determine the error-propagation paths of all possible fault candidates [1, 8]....
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Journal Article•DOI•

FPGA-based fault injection into switch-level models

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Alireza Ejlali¹, Seyed Ghassem Miremadi¹•Institutions (1)

Sharif University of Technology¹

02 Aug 2004-Microprocessors and Microsystems

TL;DR: In this method, gates model switch-level circuits and the authors can emulate mixed gate-switch-level models and FPGA chips can be used to accelerate the fault-injection campaigns into switch- level models.

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18 citations

Cites background or methods from "Digital Systems Testing and Testabl..."

...Techniques for fault injection fall into two categories: (i) simulationbased fault injection [15,23,31], i.e. fault injection into simulation models of systems, and (ii) physical fault injection [2,19,26], i.e. fault injection into physical systems (prototypes or actual systems)....
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...It should be noted that switch-level simulation (switchlevel fault injection) is more time-consuming than gate-level simulation (gate-level fault injection) [8]....
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...By operating directly on the transistor network, switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength [6,14]....
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...One advantage of simulation-based fault injection is that it can be used early in the design cycle [2,19,23]....
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Journal Article•DOI•

On the nonenumerative path delay fault simulation problem

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Dimitrios Kagaris¹, Spyros Tragoudas¹•Institutions (1)

Southern Illinois University Carbondale¹

07 Nov 2002-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

TL;DR: The problem of determining the exact number of path delay faults that a given test set detects in a combinational circuit is shown to be intractable and the importance of several recently proposed pessimistic heuristics as well as exact exponential algorithms for this nonenumerative problem is strengthened.

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Abstract: The problem of determining the exact number of path delay faults that a given test set detects in a combinational circuit is shown to be intractable. This result further strengthens the importance of several recently proposed pessimistic heuristics as well as exact exponential algorithms for this nonenumerative problem. A polynomial time pessimistic algorithm which returns higher coverage than algorithms with the same order of complexity and at the same time compacts the test set is also presented.

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18 citations

Proceedings Article•DOI•

Maximum independent sets on transitive graphs and their applications in testing and CAD

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Dimitrios Kagaris¹, Spyros Tragoudas¹•Institutions (1)

Southern Illinois University Carbondale¹

13 Nov 1997

TL;DR: A polynomial time algorithm that finds the maximum weighted independent set of a transitive graph that finds applications in a variety of VLSI contexts, including path delay fault testing, scheduling in high level synthesis and channel routing in physical design automation.

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Abstract: We present a polynomial time algorithm that finds the maximum weighted independent set of a transitive graph. The studied problem finds applications in a variety of VLSI contexts, including path delay fault testing, scheduling in high level synthesis and channel routing in physical design automation. The algorithm has been implemented and incorporated in a CAD tool for path delay fault testing. We experimentally verify its impact in the latter context.

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18 citations

Patent•

Methods for distribution of test generation programs

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Jon Udell¹, Chen Wang¹, Mark Kassab¹, Janusz Rajski¹•Institutions (1)

Mentor Graphics¹

20 Oct 2005

TL;DR: In this paper, the authors make circuit testing algorithms, or portions thereof, make distributable by isolating any random number generation therewith to be independent of each other, and this isolation applies to any number generation associated with different call instances of the same algorithm as well.

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Abstract: As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

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18 citations

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Digital Systems Testing and Testable Design

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