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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
Design for testability and testing of IEEE 1149.1 TAP controller
TL;DR: The design techniques simplify the procedure to test the TAP controller by orders of magnitude compared to previously published results and can be easily automated and incorporated into test tools.
Fault-Tolerant Computing: An Overview
TL;DR: The topics covered include module function and system-level fault detection methods, redundancy and reconfiguration strategies, valid fault models, and coding and checking in computer systems.
Proceedings ArticleDOI
Automatic Clock Abstraction from Sequential Circuits
TL;DR: This work focuses on taking a gate-level sequential circuit and performing a temporal analysis which abstracts the clocks from the circuit, which generates a cycle-level gate model with the detailed timing abstracted from the original circuit.
Optimal Sequencing of Scan l%egiste!rs*
TL;DR: A methodology to construct a single scan chain that provides dramatic reductions in test application time is presented and an algorithmic technique to generate single chain configurations that minimize the test time is provided.
Journal ArticleDOI
Chip-package Co-implementation of a triple DES Processor
TL;DR: Measurements show 3DES operation at 110 MHz, which translates to a throughput of over 7 Gb/s, the highest reported 3DES throughput to date.