Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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26 Apr 1999
TL;DR: New techniques to prove diagnostic fault equivalence are presented based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites.
Abstract: Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence.
17 citations
TL;DR: It is shown that arrays of dimension two or greater can be effectively tested for the case when the functions defined by the arrays have inverses, and that even for functions which do not satisfy this property, the functional approach simplifies testing problems considerably.
Abstract: We consider the problem of fault detection in iterative logic arrays (ILA's). This problem has been studied by numerous researchers for many years. The results can be succinctly summarized by stating that one dimensional arrays can be effectively analyzed and significant results obtained while the problems associated with arrays of dimension two or greater appear to be intractable (i.e., NP-complete) for general arbitrary ILA's. However as is the case for many other switching theory problems, general case problems that are intractable, can be readily handled for the special cases defined by functions commonly encountered in practice. We show that arrays of dimension two or greater can be effectively tested for the case when the functions defined by the arrays have inverses. Many specific arithmetic functions satisfy this property. We also show that even for functions which do not satisfy this property, the functional approach simplifies testing problems considerably. >
17 citations
26 Oct 2004
TL;DR: A simulation-based benchmarking strategy is developed that uses circuit-level models to describe the complex nature of real defects and a simple yet powerful strategy using a small circuit and a set of bounded deformations for measuring the effectiveness of diagnosis techniques.
Abstract: Diagnosis algorithms for integrated circuits (ICs) are typically developed and evaluated using a limited number of logic-level models of defect behaviors. However, it is well-known that real IC defects exhibit behavior well outside these models. Consequently, the utility of IC diagnosis methodologies may be uncertain. A simulation-based benchmarking strategy is developed that uses circuit-level models to describe the complex nature of real defects. Specifically, we have proposed a simple yet powerful strategy using a small circuit and a set of bounded deformations (i.e., defects) for measuring the effectiveness of diagnosis techniques. Evaluation of several simple and commercial diagnosis algorithms indicates that this form of diagnosis benchmarking is viable.
17 citations
Cites background from "Digital Systems Testing and Testabl..."
...can be very broadly classified into two categories cause-effect diagnosis [3]-[15] and effect-cause diagnosis [16]-[30]....
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04 Dec 2000
TL;DR: A framework that enables the computation of tight ranges of signal arrival, transition, and required times for rising and falling transitions at each circuit line, given an input sequence consisting of two partially specified vectors to reduce the amount of search required by a test generator that uses timing information.
Abstract: In this paper we present a framework that enables the computation of tight ranges of signal arrival, transition, and required times for rising and falling transitions at each circuit line, given an input sequence consisting of two partially specified vectors. At one extreme, when the vectors are completely unspecified, this framework becomes identical to static timing analysis (STA). At the other extreme, when the vectors are completely specified, this framework performs timing simulation (TS). Our key motivation for developing this framework was to reduce the amount of search required by a test generator that uses timing information. During test generation for a target fault, values are specified incrementally and this framework enables refinement of timing windows. We demonstrate that this approach significantly improves test generation efficiency. In this mode, the ATPG is said to be performing incremental timing refinement (ITR).
17 citations
Journal Article•
TL;DR: Using state space technique and GF(2) theory, a simulation model for external exclusive NOR type LFSR structures is developed and through this tool a systematic procedure is devised for computing pseudo-random binary sequences from such structures.
Abstract: — Using state space technique and GF(2) theory, a simulation model for external exclusive NOR type LFSR structures is developed. Through this tool a systematic procedure is devised for computing pseudo-random binary sequences from such structures. Keywords — LFSR, external exclusive NOR type, recursive binary sequence, initial state - next state, state transition matrix. An LFSR is made up of two parts: a shift register and a I. I NTRODUCTION INARY sequences whose terms depend in a simple manner on their predecessors are of great importance for a variety of applications. Such sequences are easily generated by recursive procedures and popularly known as with many names like Recursive Binary Sequences (RBS), Pseudo Random Binary Sequences (PRBSs), Maximal length sequences (m-sequences), and Pseudo Noise (PN) sequences [1 - 9]. Such kinds of sequences have an advantageous feature from the computational viewpoint, and they tend to have useful structural properties [10 - 19]. Due to only these structural properties, PRBSs have enormous applications for example: Direct Sequence Spread Spectrum (DSSS) [9, 20], Pseudo-random Number (PN) [1 - 20] generation, Built-in Self-Test (BIST) [21 - 40], Encryption – Decryption [41, 42] and Error Detection [3 - 5], [9] and many more. The PRBSs can be easily generated by the use of simply extended circuits of shift registers, which is popularly known as Linear Feedback Shift Registers (LFSRs). Different types of LFSR structures are being used in various applications. These structures are broadly classified as: o External Exclusive OR (EEOR), o External Exclusive NOR (EENOR), o Internal Exclusive OR (IEOR), and o External Exclusive OR (EEOR) types. Mathematical models of IEOR and EEOR structures are generously discussed in research literatures [1 – 9], [16], [18], [21], [23], [43]. But the theory and model of EENOR type of structure are not available right now although it is highly starts repeating. An example of such generated sequence is as:
17 citations