Digital Systems Testing and Testable Design
Citations
16Â citations
Cites methods from "Digital Systems Testing and Testabl..."
...At each clock cycle, the differences in the current inputs and states are propagated through the circuit according to the classical event-driven algorithm [1], in increasing order of levels....
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16Â citations
16Â citations
16Â citations
Cites methods from "Digital Systems Testing and Testabl..."
...SWK is a path-oriented decision making (PODEM)-based [27] ATPG algorithm that exploits both simulation and search-space parallelism....
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16Â citations
Cites background from "Digital Systems Testing and Testabl..."
...Classically physical defects are modeled in the gate-level representation as lines stuck at a specific logic value [9]....
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...As the miniaturization and the density of devices on VLSI chips increases, open and bridging faults become more important and requires more refined fault models (such as transition fault model [9]) to improve the accuracy of the translation of physical defects into electrical faults....
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