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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
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Proceedings Article•DOI•
26 Apr 1999
TL;DR: This paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level, based on a set of suitable testability metrics, and the test pattern Generation phase resorts to genetic algorithms.
Abstract: High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based on a set of suitable testability metrics, and the test pattern generation phase resorts to genetic algorithms. Experiments show the excellent fault coverage provided by the RT-level test patterns, when applied at the final gate-level. The approach, being based on a high-level representation, promises to be particularly suited where gate-level ATPGs are often inefficient, mainly for large circuits and for control-intensive designs.

16 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...At each clock cycle, the differences in the current inputs and states are propagated through the circuit according to the classical event-driven algorithm [1], in increasing order of levels....

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Patent•
11 Mar 2013
TL;DR: In this article, the authors propose a method of maintaining a memory state of a 3D memory, wherein the memory includes at least a first cell and a second cell overlying the first cell.
Abstract: A method of maintaining a memory state of a 3D memory, wherein the memory includes at least a first cell and a second cell overlying the first cell, the method including: applying a back-bias to the first cell and the second cell without interrupting data access to the memory, and generating at least two stable floating body charge levels of the memory state.

16 citations

Journal Article•DOI•
TL;DR: Two techniques are proposed (for non-timing-driven and timing-driven partial scan) which address the above criterion based on a transformation of sequential circuits known as retiming, which reduces the overall area overhead required to achieve the clock period bound.
Abstract: A generally effective criterion for the selection of flip-flops in the partial scan problem for sequential circuit testability is to select flip-flops that break the cyclic structure of the circuit and reduce its sequential depth. The selection of flip-flops may also be subject to a prescribed bound on the clock period of the modified circuit (timing-driven partial scan). In this paper we propose two techniques (for non-timing-driven and timing-driven partial scan) which address the above criterion based on a transformation of sequential circuits known as retiming. For non-timing-driven partial scan, we employ retiming to rearrange the flip-flops of the circuit, so that its functionality is preserved, while the number of flip-flops that are needed to break all cycles and bound the sequential depth is significantly reduced. For timing-driven partial scan, we propose a retiming-based technique that reduces the overall area overhead required to achieve the clock period bound. Experimental results on the ISCAS'89 circuits show the benefit of our approach in both timing-driven and non-timing-driven partial scan.

16 citations

Journal Article•DOI•
TL;DR: Experimental results on ISCAS'89 and IWLS'05 benchmark circuits show that SWK test sets are better in many quality metrics than traditional 50-detect test sets, while the length of the former is shorter.
Abstract: This paper proposes a bit-level parallel ATPG algorithm (SWK) that generates multiple test patterns at a time. This algorithm converts decisions into bitwise logic operation so that W (CPU word size) test patterns are searched independently. Multiple objectives for different quality metrics can therefore be achieved in a single test generation process. Experimental results on ISCAS'89 and IWLS'05 benchmark circuits show that SWK test sets are better in many quality metrics than traditional 50-detect test sets, while the length of the former is shorter. Also, patterns selected from large N-detect pattern pool cannot achieve the same or higher quality than patterns generated by SWK.

16 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...SWK is a path-oriented decision making (PODEM)-based [27] ATPG algorithm that exploits both simulation and search-space parallelism....

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Proceedings Article•DOI•
10 Mar 2008
TL;DR: L lithographic simulation based identification of potential open fault sites, identification of meta-stable input states for these open inputs, and length calculation for side channel signals for definitive detection of open faults provide a complete CAD framework for testing lithography related open faults.
Abstract: Scaling of transistor feature size over time has been facilitated by corresponding improvement in lithography technology. However, in recent times the wavelength of the optical light source used for photolithography has not scaled in the same rate as that of the minimum feature size of the transistor. In fact, starting with 180 nm devices, the wavelength of optical source has remained the same (at 193 nm) due to difficulties in finding a flicker-free, high energy, coherent light source with compatible improvement in lens material for focusing this light. Consequently, upcoming technology nodes (65 nm, 45 nm, 32 nm and 22 nm) will be using a light source with wavelength much greater than the feature size. This creates a peculiar problem where line width on manufactured devices is a function of relative spacing between adjacent lines. Despite numerous restriction on layout rules, interconnects may still suffer from constriction due to this peculiarity also known as forbidden pitch problem. A small manufacturing variation turns the constrictions to open faults. Gate leakage current is a significant concern for present and upcoming technology nodes. Due to gate leakage, an open fault is not truly an open circuit. Our simulation studies show that the leakage current steers the floating input of a gate to certain meta- stable states. This property actually makes it easier to detect open faults either through side channel excitation or by stuck-at tests. The major contributions of this paper are (i) lithographic simulation based identification of potential open fault sites, (ii) identification of meta-stable input states for these open inputs, (iii) length calculation for side channel signals for definitive detection of open faults. Together, they provide a complete CAD framework for testing lithography related open faults.

16 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Classically physical defects are modeled in the gate-level representation as lines stuck at a specific logic value [9]....

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  • ...As the miniaturization and the density of devices on VLSI chips increases, open and bridging faults become more important and requires more refined fault models (such as transition fault model [9]) to improve the accuracy of the translation of physical defects into electrical faults....

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