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Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: Experimental results demonstrate that, even when a test set has minimum or close-to-minimum size, the use of a complementation vector allows us to reduce the size of the stored test set further, and almost always below the known lower bound on the size.
Abstract: Both test compaction and test data compression methods provide an opportunity for a tester to apply modified versions of each test, in addition to the original test. We take advantage of this opportunity to achieve additional test data volume reductions. One way to modify a test is to complement some or all of its bits. We represent the way in which modified tests will be obtained by a complementation vector. Experimental results demonstrate that, even when a test set has minimum or close-to-minimum size, the use of a complementation vector allows us to reduce the size of the stored test set further, and almost always below the known lower bound on the size of a test set. The use of a complementation vector is equivalent to a modulo-2 addition operation. We generalize it to modulo- M addition, for a constant M ≥ 2. With modulo-M addition, each stored test yields up to M tests. It is thus possible to reduce the size of the stored test set even further.
15 citations
TL;DR: This work considers the problem of checking whether an incomplete design can still be extended to a complete design satisfying a given property or whether the property is satisfied for all possible extensions and presents an approximate, yet sound algorithm to process incomplete designs.
Abstract: We consider the problem of checking whether an incomplete design (i.e., a design containing "unknown parts", so-called Black Boxes) can still be extended to a complete design satisfying a given property or whether the property is satisfied for all possible extensions. There are many applications of property checking for incomplete designs, such as early verification checks for unfinished designs, error localization in faulty designs and the abstraction of complex parts of a design in order to simplify the property checking task. To process incomplete designs we present an approximate, yet sound algorithm. The algorithm is flexible in the sense that for every Black Box a different approximation method can be chosen. This permits us to handle less relevant Black Boxes (in terms of the property) with larger approximation and thus faster, whereas we do not lose important information when the possible effect of more relevant Black Boxes is modeled by more exact methods. Additionally, we present a concept to decide exactly whether Black Boxes with bounded memory can be implemented so that they satisfy a given property. This question is reduced to conventional symbolic model checking. The effectiveness and feasibility of the methods is demonstrated by a series of experimental results.
15 citations
Additional excerpts
...Symbolic Z-simulation is motivated by the well-known (0, 1, X)simulation [14], [20], [21]....
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TL;DR: An empirical analysis shows that the workload distribution is circuit specific, and is largely independent of the vector set being simulated, and an inexpensive method to predict the workload distribution is discussed.
Abstract: Simulation at the gate level is computationally very expensive Parallel processing is one technique to reduce simulation time Possessing knowledge of the distribution of computational activity in simulation can aid in parallelizing it efficiently We present a new characterization of the distribution of the computational workload in fault simulation An empirical analysis shows that the workload distribution is circuit specific, and is largely independent of the vector set being simulated An inexpensive method to predict the workload distribution is also discussed
15 citations
Cites background from "Digital Systems Testing and Testabl..."
...1 Introduction Fault simulation is used in a number of test applications [1]....
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...Several implementations are possible for parallel fault simulators [1]....
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05 Nov 2012
TL;DR: Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate that early-life and wear-out failures can be accurately diagnosed with minimum overhead using TRAX dictionaries that are up to 2600x smaller than full-response dictionaries.
Abstract: One approach for achieving integrated-system robustness centers on performing test during runtime, identifying the location of any faults (or potential faults), and repairing or avoiding the affected portion of the system. Fault dictionaries can be used to locate faults but conventional approaches require significant memory storage and are therefore limited to simplistic fault types. To overcome these limitations, three contributions are made that include: (i) enhancement of an unspecified transition fault model (called here the transition-X fault model, or TRAX for short) for capturing the misbehaviors expected from scaled technologies, (ii) development of a new type of hierarchical dictionary that only localizes to the level of repair or fault avoidance, and (iii) the design of a scalable architecture for retrieving and using the hierarchical dictionary for performing on-chip diagnosis. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate that early-life and wear-out failures can be accurately diagnosed with minimum overhead using TRAX dictionaries that are up to 2600x smaller than full-response dictionaries.
15 citations
01 Aug 2017
TL;DR: An efficient technique for the detection of malicious hardware, based on thermal sensors, using a 64-bit Linear Feedback Shift Register for Hardware Trojan Detection is introduced.
Abstract: This paper introduces an efficient technique for the detection of malicious hardware, based on thermal sensors. Each sensor consists of a Ring Oscillator with three inverters, a control multiplexer and a compact Residue Number System ring counter requiring only two FPGA slices. The sensors were placed in a 6x5 grid structure in equal distance from each other, in order to cover the whole area of the FPGA implementation causing a total overhead of only 1.9 %. To emulate a Hardware Trojan, a 64-bit Linear Feedback Shift Register was used. We demonstrate the proposed technique with an experimental system based on a XILINX Basys 3 board. The results from the experiments illustrate the efficiency of the proposed technique. According to our knowledge we are the first that we have used this kind of sensor for Hardware Trojan Detection.
15 citations
Cites methods from "Digital Systems Testing and Testabl..."
...The LFSR is enabled by using the clock gated in order to be able to only observe the impact of the additional gated while there is no switching activity of the LFSR itself when is inactive....
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...The LFSR was placed all around the sensor 9 (Line 2, Column 4)....
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...The final layout is shown in Figure 3 with the 30 thermal sensors (yellow color) and the 64-bit LFSR as HT (blue color)....
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...The second is the Linear Feedback Shift Register counter (LFSR counter), which in modern FPGAs can be implemented using shift register LUTs (SRLs) thus leading to a very compact design....
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...As an HT, a 64-bit Linear Feedback Shift Register (LFSR) [21] was implemented similar to [11]....
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