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Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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16 Nov 1996
TL;DR: This approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures and shows that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one.
Abstract: Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-in Self-Test) techniques is increasingly popular, but sometimes requires efficient algorithms for the automatic generation of the logic which generates the test vectors applied to the unit under test. This paper addresses the issue of identifying a cellular automaton able to generate input patterns to detect stuck-at faults inside a finite state machine (FSM). A suitable hardware structure is first identified. A genetic algorithm is then proposed, which directly identifies a cellular automaton able to reach a very good fault coverage of the stuck-at faults. The novelty of the method consists in combining the generation of test patterns with the synthesis of a cellular automaton able to reproduce them. Experimental results are provided, which show that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one. Our approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures.
15 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Built-In Self-Test (BIST) [ ABFr90 ] has been widely recognized as an effective approach for testing of Application Specific Integrated Circuits (ASICs)....
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TL;DR: A compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system for embedded SRAM cores is proposed, which provides programmability for custom March algorithms with lower hardware cost.
Abstract: In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.
15 citations
Cites methods from "Digital Systems Testing and Testabl..."
...The fault dictionary is constructed from the simulated responses under the given test algorithm and fault models [1]....
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01 Jun 1996
TL;DR: A new procedure is described for estimating the delay-dependent switching activities in CMOS combinational circuits based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators.
Abstract: This paper describes a new procedure for estimating the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators. Combinational circuits driven by synchronized logic signals are considered as application targets and the statistical properties of logic signals and circuit parameters are defined and evaluated. The experimental result on benchmark circuits shows the significant time efficiency of the proposed procedure.
15 citations
Cites background from "Digital Systems Testing and Testabl..."
...Therefore, one important requirement of the combinational circuit is the long path timing constraint, which requires that the actual delay of the circuit is not longer than a timing requirement T, usually the clock period [9]....
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TL;DR: A brief review of test algorithms successfully using the capabilities of DDs as a data structure for tasks like fault detection, synchronization and built-in-self-test using DD manipulation algorithms.
15 citations
20 Apr 2009
TL;DR: A scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits and guides the justification and propagation decisions to create patterns that will accommodate most targeted faults.
Abstract: This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern sets for ISCAS circuits. For industrial circuits it achieves much smaller test pattern sets than other methods in designs sensitive to decision order used in ATPG.
15 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Some of these methods do not alter the tests in the set [1][11]....
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...Terms related to test generation procedures and used later in the paper are defined below [1]....
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