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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Journal Article•DOI•
TL;DR: In this article, the authors examine the developments in IC testing from the historic, current status and future view points and relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.
Abstract: Integrated circuit (IC) testing for quality assurance is approaching 50% of the manufacturing costs for some complex mixed-signal ICs. For many years the market growth and technology advancements in digital ICs were driving the developments in testing. The increasing trend to integrate information acquisition and digital processing on the same chip has spawned increasing attention to the test needs of mixed-signal ICs. The recent advances in wireless communications indicate a trend toward the integration of the RF and baseband mixed signal technologies. In this paper we examine the developments in IC testing from the historic, current status and future view points. In separate sections we address the testing developments for digital, mixed signal and RF ICs. With these reviews as context, we relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.

105 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...The general structure of a digital circuit using BIST is shown in Fig. 23. Response verification in BIST is usually done by comparing the response of one part of the circuit, with the response from another part (in the case of regular circuits), or using feedback shift registers acting as signature analyzers [ 13 ], or some combination of the two....

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Journal Article•DOI•
TL;DR: Extensive experimental results demonstrate better performance of the proposed scheme over popular classification algorithms in respect of memory overhead and retrieval time with comparable classification accuracy.
Abstract: This paper presents the theory and application of a high speed, low cost pattern classifier. The proposed classifier is built around a special class of sparse network referred to as Cellular Automata (CA). A specific class of CA, termed as Multiple Attractor Cellular Automata (MACA), has been evolved through Genetic Algorithm (GA) formulation to perform the task of pattern classification. The versatility of the classification scheme is illustrated through its application in three diverse fields - data mining, image compression, and fault diagnosis. Extensive experimental results demonstrate better performance of the proposed scheme over popular classification algorithms in respect of memory overhead and retrieval time with comparable classification accuracy. Hardware architecture of the proposed classifier has been also reported.

105 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Use of fault dictionaries is a probable solution for the diagnosis process, particularly when repeated diagnosis is required for different copies of the s ame circuit [1, 3, 4]....

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Journal Article•DOI•
TL;DR: A serial fault emulation algorithm enhanced by two speed-up techniques that uses the field programmable gate array (FPGA)-based emulation system for fault grading and shows that this approach could be several orders of magnitude faster than the existing software approaches for large sequential designs.
Abstract: In this paper, we introduce a method that uses the field programmable gate array (FPGA)-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the performance of fault grading, which is one of the most time consuming tasks in the circuit design and test process. We employ a serial fault emulation algorithm enhanced by two speed-up techniques. First, a set of independent faults can be injected and emulated at the same time. Second, multiple dependent faults can be simultaneously injected within a single FPGA-configuration by adding extra circuitry. Because the reconfiguration time of mapping the numerous faulty circuits into the FPGA's is pure overhead and could be the bottleneck of the entire process, using extra circuitry for injecting a large number of faults can reduce the number of FPGA-reconfigurations and, thus, improving the performance significantly. In addition, we address the issue of handling potentially detected faults in this hardware emulation environment by using the dual-railed logic. The performance estimation shows that this approach could be several orders of magnitude faster than the existing software approaches for large sequential designs.

104 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Definition 2 [3]: A set of faults is called (structurally) independentas long as the output images of the faults in are mutually disjoint....

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Proceedings Article•DOI•
27 Apr 2003
TL;DR: An efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic scan) architecture is defined and the results demonstrate the efficiency of the proposed architecture for real-industrial circuits.
Abstract: In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

104 citations

Journal Article•DOI•
B. Chess1, T. Larrabee•
TL;DR: This work demonstrates that if information is removed from a fault dictionary, its ability to diagnose unmodeled faults may be severely curtailed even if dictionary quality metrics remain unaffected; it presents a new dictionary organization based on error sets, which is amenable to standard data-compression techniques.
Abstract: Diagnostic fault simulation can generate enormous amounts of data. The techniques used to manage this data can have significant effect on the outcome of the fault diagnosis procedure. We first demonstrate that if information is removed from a fault dictionary, its ability to diagnose unmodeled faults may be severely curtailed even if dictionary quality metrics remain unaffected; we, therefore, focus on methods for producing small, lossless dictionaries, We present a new dictionary organization based on error sets, which is amenable to standard data-compression techniques. We compare several dictionary organizations and the effect of standard data-compression techniques on each of them. An appropriate organization and encoding makes dictionary-based diagnosis practical for very large circuits.

102 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Boppana, Hartanto, and Fuchs have suggested a family of organizations based on diagnostic trees [ 1 ], [6]....

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