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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
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Journal Article•DOI•
TL;DR: A framework for diagnostic fault simulation and test generation is described, based on structural circuit characteristics called z-sets, to show that certain fault pairs are guaranteed to be distinguished by a fault detection test set.
Abstract: Diagnostic fault simulation is used to determine the pairs of faults distinguished by a given test set or test sequence. Diagnostic test generation is used to generate tests that distinguish pairs of faults. Typically, the test sets or test sequences contain tests that detect all the detectable target faults. In this paper, a framework for diagnostic fault simulation and test generation is described, based on structural circuit characteristics called z-sets. These characteristics are used to show that certain fault pairs are guaranteed to be distinguished by a fault detection test set. Such fault pairs do not need to be considered during diagnostic fault simulation or test generation that starts from a fault detection test set. Experimental results for single stuck-at faults in full-scan benchmark circuits demonstrate that only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. The concept of -sets is extended to define z-detections. This concept uses the results of conventional fault simulation to determine additional fault pairs that are guaranteed to be distinguished by a fault detection test set. The concept of z-sets is also extended to define difference-sets (or d-sets) that provide even fewer targets for diagnostic test generation.

13 citations

Journal Article•DOI•
TL;DR: By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDE1.
Abstract: In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDE1. This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.

13 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...1 Instead of an AND-gate all logic functions with controlling values can be used [ 1 ]....

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Proceedings Article•DOI•
21 Oct 1995
TL;DR: A class of redundant faults that naturally derive from the structure and behavior of these filters are examined, and design-for-test (DFT) techniques based on scaling theory are used to eliminate the redundancies.
Abstract: Testability problems that arise in the design of fixed-coefficient finite impulse response (FIR) filters are examined. A class of redundant faults that naturally derive from the structure and behavior of these filters are examined, and design-for-test (DFT) techniques based on scaling theory are used to eliminate the redundancies. Eliminating these redundancies makes it possible for built-in self-test (BIST) approaches to reach 100% coverage, and automatic test-pattern generation (ATPG) based approaches can benefit by more than an order of magnitude reduction in test generation time. A case study provides a demonstration of the approach.

13 citations

Proceedings Article•DOI•
28 Apr 1996
TL;DR: The number of test points needed to achieve complete testability is reduced by ensuring that test points are inserted only on paths associated with path delay faults that are necessary to be tested and that are not robustly testable.
Abstract: Recently, Pomeranz and Reddy (1994), presented a test point insertion method to improve path delay fault testability in large combinational circuits. A test application scheme was developed that allows test points to be utilized as primary inputs and primary outputs during testing. The placement of test points was guided by the number of paths and was aimed at reducing this number. Indirectly, this approach achieved complete robust path delay fault testability in very low computation times. In this paper, we use their test application scheme, however, we use more exact measures for guiding test point insertion like test generation and RD fault identification. Thus, we reduce the number of test points needed to achieve complete testability by ensuring that test points are inserted only on paths associated with path delay faults that are necessary to be tested and that are not robustly testable. Experimental results show that an average reduction of about 70% in the number of test points over the approach of Pomeranz and Reddy can be obtained.

13 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...primary output to improve the observability of embedded parts of a circuit [ 25 ]....

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Patent•
17 Apr 2001
TL;DR: In this paper, a fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided, where a user's design is modeled, and the user's logic design is then modified, thereby facilitating the detection of faults.
Abstract: Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

13 citations